JVC FS-SD7R - Page 26

FS-SD5R/FS-SD7R/FS-SD9R
i MN35510(IC603):Digital servo & Digital signal processer
1. Terminal Layout
20 ~ 1
21 80
2 t
40 61
41 ~ 60
2.Block Diagram
a Hy .
LRCKIN(MSEL) | > ~—] avssi
BCLK(SSEL) | > STIMES TW “<— avoo1
SRDATAIN *| DIGITAL |__| OVER SAMPUNC >| OUTR
(PSEL) Wn DEEMPHSIS DIGITAL FILTER ESlanans
| es
IOSEL
|
HS
CLVS |~«—+ |
CRC |~«
BLKCK >|OUTL
CLDCK |« SS
sos
BC |~«—+ \
DEMPH
|<j——
|
|
a
RESY
FLAG6(RESY) _]
| FLAG
IPFLAG
EFM DIGITAL
DEMODULATION AUDIO 1X
INTERFASE
SYNC
INTERPOLATION
DIGITAL
ECM
suscove | | tao [||
DEMODULATION INTERFASE PC
CIRC
ERROR
CORRECTION
oa
INTER
POLATION
aicl
LRCK
DEINTERLEVE SOFT MUTING DIGITAL SRDATA
PSEL [—"] ATTENUATION BCLK
PEAK DETECTIVE DMUTE
MOLE AUTO CUE
MDATA | | >ITRKV
‘Se ee | KICK
384(EFM) <4 SSE
Vere
e
uO
MICRO
CLV
>|TRVSTR
BYTCK
|<—
cui
aal
deed
SERVO
>lECS
SMCK INTERFACE D/A >ITVD
FOLK
=
ITUNING
/
ala
CSEL
GENERATION
CONVERTER
SIERe
MSEL }-—+ PITCH >ITBAL
X2 -—- CONTROL >| BAL
X1 + >|TOFS
: TES
ESTAT™ »|'TLOCK
>|IFLOCK
OUTPUT PORT >|>LAY
>|_ DON
>WVEL
>|SENSE
AID INPUT SERVO
COVERTER TIMING GENERATOR
VV DDI / F oT R T VB / re)
DS VVAT E E F R D OD R F
DS DSSE E CE -:0 F T
DSTS N R T D
11 T Vv s E
2-14