JVC GZ-MG20EK - Page 15

(No.YF108)2-27 2-28(No.YF108)
IC5501
JCY0185
(TG/V_DRIVER)
1
CS/SEN
2
CLK/SSK
3
DATA/SSI
4
Vdd1
5
VGAT
6
DSGAT
7
HCLR
8
RG
9
Vss1
10
Vdd2(RG)
11
H1
12
Vdd3(H)
13Vss2
14H2
15Vss3
16Vdd4(CDS)
17SHP
18SHD
19XRS
20DCC
21Vss4
22CLK18/MCK
23CAM/VTR
24Vdd5
25
CK
26
SSGCTL
27
PBLK
28
CLMDM
29
Vss5
30
XAHD
31
XAVD
32
OBCLP
33
WEN
34
ID
35
CLK27/CLK1716
36
Vdd6
37 CLK13/CL
38 TEST
39 VM
40 V2
41 V4
42 V1
43 VH
44 V3
45 SUB
46 VL
47 Vss6
48 RST
R5511
100k
D5501
1SS355-X
T
C5514
1/35
R5501 R5502 R5503
R5504
10
R5505
10
R5506
10
R5508
10
R5507
10
R5509
10
C5501
0.1
C5502
0.1
C5503
0.1
C5504
0.1
C5507
0.1
C5510
0.1
T
C5505
10/6.3
L5502
NQR0129-002X
L5501
10µ
L5506
10µ
L5505
NQR0129-002X
L5508
10µ
L5507
NQR0129-002X
C5513
0.1
C5515
0.1
C5517
0.1
C5518
0.1
C5511
0.1
C5520
0.1
T
C5519
47/4
T
C5512
4.7/25
T
C5516
10/16
C5509
0.1
C5508
0.1
L5504
NQR0129-002X
X5501
NAX0587-001X
(54MHz_CXO)
1
CTL
2
GND
3
OUT
4
VDD
CCD_CTL
TG2_RST
TG_CS
CAM_OUT
CAM_3.1V
REG+CCD
GND
REG-CCD
CDS_3V
SHD
SHP
ADCLK
PBLK
MCLKI
TG_ID
TG_VD
TG_HD
CAM_CLK
OBCLP
R5510
10
IC5502
(3.3V_REG)
1
VIN
2
GND
3
CTL
4
NOISE
5
VOUT
REG_4.8V
C5522
P_GYAMP
REG_3.1V
G_RST
GND
IC5503
(3.0V_REG)
1
VIN
2
GND
3
CTL
4
NOISE
5
VOUT
C5524
C5525C5526
R5513
R5515
10
R5516
10
R5517
10
R5518
10
R5514
10
TO CCD(CN5001)
CN105
QGF0547C2-24X
1REG+CCD
2REG+CCD
3REG-CCD
4REG-CCD
5CCD_CTL
GND
GND
GND
CCD_OUT
GND
GND
GND
13RG
14H1
15H2
16SUB
17V1
18V2
19V3
20V4
21GND
22G_RST
23REG_3.1V
24P_GYAMP
TL5001
C5506
L5503
NQR0129-002X
R5519
R5512
C5521
C5523
0Ω 0Ω 0Ω
0Ω
y30328001a_rev0.1
MAIN(TG068)
10
TO P.PRCS
TO SUB CPU
TO CDS,
P.PRCS,
OP DRV
TO P.PRCS
TO P.PRCS
TO P.PRCS,
GYRO
TO DSP
TO CDS
TO CDS
TO MAIN IF
(CN101,CN103),CDS
TO MAIN IF,V I/O
TO MAIN IF(CN103)
MAIN(TG068) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.