JVC TH-A5R - DVD Playback Features; On-Screen Bar Information; Subtitle and Audio Language Selection

TH-A5R
1-31
3. Block diagram
1. Pin layout
2. Pin function
CS8415A (DIC14) : Digital audio receiver
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
RXP1
RXP2
RXP3
SCL/CCLK
AD1/CDIN
RXP6
RXP5
H/S
VD+
DGND
OMCK
U
INT
SDOUT
OLRCK
OSCLK
RXP4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Symbol
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
RXP1,RXP2
RXP3,RXP4
RXP5,RXP6
OSCLK
OLRCK
SDOUT
INT
U
OMCK
DGND
VD+
H/S
AD1/CDIN
SCL/CCLK
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12,13
14,15
25,26
16
17
18
19
20
21
22
23
24
27
28
I/O
I/O
I/O
O
I
I
I
O
O
I/O
O
I
I/O
I/O
O
O
O
I
I
I
I
I
I
RSN0
VA+ VD+AGND
Receiver
H/S
DGND
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
7:1
MUX
C&U bit
Data
Buffer
Misc.
Control
FILT RERR RMCK OMCK
RST
EMPH
U
SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/
CS
INT
OLRCK
OSCLK
SDOUT
Clock &
Data
Recovery
Control
Port &
Registers
AES
S/PDIF
Decoder
Serial
Audio
Output
Function
Serial Control Data I/O(I2C) / Data Out(SPI)
Address Bit 0(I2C) / Control Port Chip Select(SPI)
Pre-Emphasis
AES3/SPDIF Receiver Power
Positive Analog Power
Analog Ground
PLL Loop Filter
Reset
Input Section Recovered Master Clock
Receiver Error
Additional AES3/SPDIF Receiver Port
Serial Audio Output Bit Clock
Serial Audio Output Left/Right Clock
Serial Audio Output Data
Interrupt
User Data
System Clock
Digital Ground
Positive Digital Power
Hardware/Sofrware Mode Control
Address Bit 1(I2C) / serial Control Data in (SPI)
Control Port Clock