JVC TK-C600 - Page 33

Mi MN5216 [MATSUSHITA]
(Timing Generator)
VDD
TEST
LSWCON
IRS2IRS2
IRS1
SP2
SP1
SPI
SPO
VDDI
VSsi
DS2
DS1
TEST
TEST
RWI
RWO
TEST
NR
VDD
CCDV
TRANSFER
PULSE GEN.
PULSE GEN.
SPO oom
SPI oa
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H-LATE V-LATE
COUNTER COUNTER V-COUNTER
ro
CCD H DRIVE
CPOB
CSYNC
PBLK
HCL
MN 5 2 af 6 VDDI
vss!
CLR
VR
IESW
EXTCLK
TVM
FCK
FCK2i
FCK20
VDD
n mal
g 8 a s 5 x
SS g g a
O-O C) O—-O—O
COMPARATOR
H- a
a
H-LATE
DECODER
GATE PULSE
for VSUB
V- i |
DECODER
=x
Q
pe
a
18d
gNSA
Pin function
v1
v2
v3
v4
CH1
CH2
VSUB
OSCCON
SMD1
SMD2
SMD3
ivss
VDD
FCK20
FCK2I
|FCK
VM
|EXTCLK
IESW
VR
17
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@R reset pulse 1
Pixels of CCD switching
Restrict accumulation time (1/16000sec restriction: H)
¢@H1 transfer pulse
@H2 transfer pulse
+.5V power supply
GND
o0o0o000-.0 0 90
¢V 1 transfer pulse
gV 2 transfer pulse
gV3 transfer pulse
¢V4 transfer pulse HG
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Charge pulse 1 CFMO
Charge pulse 2 TEST
VSUB pulse TEST
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HINT. OSCCON: Hi-Z EXT. OSCCON: L TEST
Shutter mode 1 TEST
Shutter mode 2 TEST
Shutter mode 3 TEST
|GND vss
+5V power supply VDD
Crystal oscillation output TEST
Crystal oscillation input LSWCON
FCK clock output IRS2
TV mode IRS1
'EXT. clock input (Not used: L or OPEN) SP2
INT./EXT. sync switching SP1
VR reset pulse input SPi
Clear input (Usually: H or OPEN) SPO
GND for INT. cell VDDI
Power supply for INT. ceil VSssli
¢H clear pulse DS2
Composite blanking DS1
Pre-blanking pulse TEST
Composite sync TEST
OB clamp pulse RWI
‘Clamp pulse 1 RWO
Clamp pulse 2 TEST
Birst flag pulse NR
+5V power supply
17
ee
GND 41 |VSS | |GND
BLC pulse 2
BLC pulse 1
Wide blanking pulse
Wide HD pulse
HD pulse
VD: pulse
Field index
Line switch pulse
GND
+5V power supply
Distinguish color line output
Color flame output
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
GND
+5V power supply
Test pin (Usually: OPEN)
Line switch control input
Iris control input 2
Iris control input 1
Sampling pulse 2
Sampling pulse 1
ADJ. SP phase input
ADJ. SP phase output
Power supply for INT. cell
GND for INT. cell
CDS pulse 2
CDS pulse 1
Test pin (Usually: OPEN)
Test pin (Usually: OPEN)
@R width ADJ. input
@R width ADJ. output
Test pin (Usually: OPEN)
@R reset pulse 2
+5V power supply
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