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Lantronix DSTni DSTni-EX - User Manual
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Part Number 900-335
Revision A 3/04
DSTni-EX User Guide
Section Five
2
Table of Contents
Main Page
Default Chapter
3
Copyright and Trademark
3
Warranty
4
Table of Contents
5
List of Tables
6
1 : about this User Guide
9
Intended Audience
10
Conventions
10
Navigating Online
10
Organization
11
2 : SPI Controller
12
Theory of Operation
12
SPI Background
12
Dstni SPI Controller
12
SPI Controller Register Summary
13
Table 2-1. SPI Controller Register Summary
13
SPI Controller Register Definitions
14
SPI_DATA Register
14
Table 2-2. SPI_DATA Register
14
Table 2-3. SPI_DATA Register Definitions
14
CTL Register
15
Table 2-4. CTL Register
15
Table 2-5. CTL Register Definitions
15
SPI_STAT Register
16
Table 2-6. SPI_STAT Register
16
Table 2-7. SPI_STAT Register Definitions
16
SPI_SSEL Register
17
Table 2-8. SPI_SSEL Register
17
Table 2-9. SPI_SSEL Register Definitions
17
Table 2-10. BCNT Bit Settings
17
DVD_CNTR_LO Register
18
Dvd_Cntr_Hi
18
Table 2-11. DVD_CNTR_LO Register
18
Table 2-12. DVD_CNTR_LO Register Definitions
18
Table 2-13. DVD_CNTR_HI Register
18
Table 2-14. DVD_CNTR_HI Register Definitions
18
100 C Controller
19
Features
19
Block Diagram
20
Theory of Operation
20
I 2 C Background
20
Figure 3-1. Dstni I C Controller Block Diagram
20
I 2 C Controller
21
Operating Modes
21
Table 3-1. Master Transmit Status Codes
22
Table 3-2. Codes after Servicing Interrupts (Master Transmit)
23
Table 3-3. Status Codes after each Data Byte Transmits
24
Table 3-4. Master Receive Status Codes
25
Table 3-5. Codes after Servicing Interrupt (Master Receive)
26
Table 3-6. Codes after Receiving each Data Byte
27
Bus Clock Considerations
29
Programmer's Reference
30
C Controller Register Summary
30
Table 3-7. I 2 C Controller Register Summary
30
I 2 C Controller Register Definitions
31
Slave Address Register
31
Table 3-8. Slave Address Register
31
Table 3-9. Address Register Definitions
31
Data Register
32
Table 3-10. Data Register
32
Table 3-11. Data Register Definitions
32
Control Register
33
Table 3-12. Control Register
33
Table 3-13. Control Register Definitions
33
Status Register
34
Table 3-14. Status Register
34
Table 3-15. Status Register Definitions
35
Table 3-16. Status Codes
35
Clock Control Register
36
Table 3-17. Clock Control Register
36
Table 3-18. Clock Control Register Definitions
36
Extended Slave Address Register
37
Software Reset Register
37
Table 3-19. Extended Slave Address Register
37
Table 3-20. Extended Slave Address Register Definitions
37
Table 3-21. Software Reset Register
37
Table 3-22. Software Reset Register Definitions
37
4 : USB Controller
38
Features
38
Theory of Operation
39
USB Background
39
USB Interrupt
39
USB Core
39
USB Hardware/Software Interface
40
Figure 4-1. Buffer Descriptor Table
41
Table 4-1. USB Data Direction
42
Table 4-2. 16-Bit USB Address
42
Table 4-3. 16-Bit USB Address Definitions
42
Table 4-4. BDT Data Used by USB Controller and Microprocessor
43
Table 4-5. USB Buffer Descriptor Format
43
Table 4-6. USB Buffer Descriptor Format Definitions
44
USB Transaction
45
Figure 4-2. USB Token Transaction
45
USB Register Summary
46
Table 4-7. USB Register Summary
46
USB Register Definitions
47
Interrupt Status Register
47
Table 4-8. Interrupt Status Register
47
Table 4-9. 16- Interrupt Status Register Definitions
47
Error Register
49
Table 4-10. Error Interrupt Status Register
49
Table 4-11. 16- Error Interrupt Status Register Definitions
49
Status Register
51
Table 4-12. Status Register
51
Table 4-13. Status Register Definitions
51
Address Register
53
Table 4-14. Address Register
53
Table 4-15. 16- Address Register Definitions
53
Frame Number Registers
54
Table 4-16. Frame Number Register
54
Table 4-17. Frame Number Register Definitions
54
Token Register
55
Table 4-18. Token Register
56
Table 4-19. Token Register Definitions
56
Table 4-20. Valid PID Tokens
56
Endpoint Control Registers
57
Table 4-21. Endpoint Control Registers
57
Table 4-22. Endpoint Control Register Definitions
57
Host Mode Operation
58
Table 4-23. Endpoint Control Register Definitions
58
Sample Host Mode Operations
59
Figure 3. Enable Host Mode and Configure a Target Device
59
Figure 4. Full-Speed Bulk Data Transfers to a Target Device
60
USB Pull-Up/Pull-Down Resistors
61
Figure 4-5. Pull-Up/Pull-Down USB
61
USB Interface Signals
62
5 : CAN Controllers
63
CANBUS Background
64
Data Exchanges and Communication
64
Arbitration and Error Checking
64
CANBUS Speed and Length
65
Features
65
Table 5-1. Bit Rates for Different Cable Lengths
65
Theory of Operation
66
CAN Register Summaries
66
Register Summary
66
Table 5-2. CAN I/O Address
66
Table 5-3. CAN Channel Register Summary
66
Detailed CAN Register Map
68
Table 5-4. Detailed CAN Register Map
68
CAN Register Definitions
71
TX Message Registers
71
Figure 5-1. TX Message Routing
71
Tx Message Registers
72
Table 5-5. Txmessage_0:Id28
72
Table 5-6. Txmessage_0:Id12
72
Table 5-7. Txmessage_0:Data 55
72
Table 5-8. Txmessage_0:Data 39
72
Table 5-9. Txmessage_0:Data 23
72
Table 5-10. Txmessage_0:Data 7
72
Table 5-11. Txmessage_0:Rtr
72
Table 5-12. Txmessage_0:Ctrl Flags
73
Table 5-13. Txmessage_0 Register Definitions
73
RX Message Registers
74
Figure 5-2. RX Message Routing
74
Rx Message Registers
75
Table 5-14. Rxmessage:id28
75
Table 5-15. Rx Message: ID28 Register Definitions
75
Table 5-16. Rxmessage:id12
75
Table 5-17. Rx Message: ID12 Register Definitions
75
Table 5-18. Rx Message: Data 55
75
Table 5-19. Rx Message: Data 55 Register Definitions
75
Table 5-20. Rx Message: Data 39
76
Table 5-21. Rx Message: Data 39 Register Definitions
76
Table 5-22. Rx Message: Data 23
76
Table 5-23. Rx Message: Data 23 Register Definitions
76
Table 5-24. Rx Message: Data 7
76
Table 5-25. Rx Message: Data 7 Register Definitions
76
Table 5-26. Rxmessage: RTR
77
Table 5-27. Rx Message: RTR Register Definitions
77
Table 5-28. Rx Message: Msg Flags
77
Table 5-29. Rx Message: Msg Flags Register Definitions
77
Error Count and Status Registers
78
Table 5-30. Tx/Rx Error Count
78
Table 5-31. Tx\Rx Error Count Register Definitions
78
Table 5-32. Error Status
78
Table 5-33. Error Status Register Definitions
78
Table 5-34. Tx/Rx Message Level Register
79
Table 5-35. Tx/Rx Message Level Register Definitions
79
Interrupt Flags
80
Table 5-36. Interrupt Flags
80
Table 5-37. Interrupt Flag Definitions
80
Interrupt Enable Registers
81
Table 5-38. Interrupt Enable Registers
81
Table 5-39. Interrupt Enable Register Definitions
81
CAN Operating Mode
82
Table 5-40. Interrupt Enable Registers
82
Table 5-41. Interrupt Enable Register Definitions
82
CAN Configuration Registers
83
Table 5-42. Bit Rate Divisor Register
83
Table 5-43. Bit Rate Divisor Register Definitions
83
Figure 5-3. CAN Operating Mode
83
Table 5-44. Configuration Register
84
Table 5-45. Configuration Register Definitions
84
Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships
85
Acceptance Filter and Acceptance Code Mask
86
Table 5-46. Acceptance Filter Enable Register
86
Table 5-47. Acceptance Filter Enable Register Definitions
86
Table 5-48. Acceptance Mask 0 Register
86
Table 5-49. Acceptance Mask 0 Register Definitions
86
Table 5-50. Acceptance Mask Register: ID 12
87
Table 5-51. Acceptance Mask Register: ID12 Definitions
87
Table 5-52. Acceptance Mask Register: Data 55
87
Table 5-53. Acceptance Mask Register: Data 55 Definitions
87
Table 5-54. Acceptance Code Register
88
Table 5-55. Acceptance Code Register Definitions
88
Table 5-56. Acceptance Mask Register: ID12
88
Table 5-57. Acceptance Mask Register: ID12 Definitions
88
Table 5-58. Acceptance Mask Register: Data 55
88
Table 5-59. Acceptance Mask Register: Data 55 Definitions
88
Canbus Analysis
89
Table 5-60. Arbitration Lost Capture Register
89
Table 5-61. Arbitration Lost Capture Register Definitions
89
Table 5-62. Error Capture Register
90
Table 5-63. Error Capture Register Definitions
90
Table 5-64. Frame Reference Register
91
Table 5-65. Error Capture Register Definitions
91
CAN Bus Interface
92
Interface Connections
92
Figure 5-5. CAN Bus Interface
92
Figure 5-6. CAN Connector
92
Figure 5-7. Power for CAN
93
Figure 5-8. CAN Transceiver and Isolation Circuits
94
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Lantronix DSTni DSTni-EX Specifications
General
Brand
Lantronix
Model
DSTni DSTni-EX
Category
Computer Hardware
Language
English
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