MC-1 Service Manual
5-4
The dots decrement in number from both sides simultaneously, as the rest of the power on diagnostic tests
are completed. This keeps a user informed as to the functioning of the MC-1.
The power on diagnostic tests are intended to verify basic hardware functionality of the MC-1. Due to the
limited time allowed to run the power on diagnostic tests, they cannot completely test all the hardware nor
can they fully diagnose a failure. Additional diagnostic tests are available for manufacturing and customer
service to completely test the hardware, and for debugging failures.
A listing of the power on tests is given first, followed by an explanation of the test. The number preceding
the test will be the test number used to display any pass or failed message. Initially, an attempt is made to
illuminate the VFD and front panel LEDs for approximately three seconds, and then the following
diagnostics will be executed:
E1 Z80 CPU Test.
E2 EPROM Checksum Test.
E3 Z80 SRAM Test, (Non-Volatile Section Saved).
E4 VFD Test.
E5 Z80 System Interrupt Timer Test.
E6 Lexichip II WCS and Word Clock Test.
E7 Lexichip II DRAM Test.
E8 56004 SPI (Serial Peripheral Interface) Test.
E9 AC3 MEM / DTS AC3MEM.
E10 DTS 56K Test.
E11 RS232 I/O Test
If a failure occurs, the test will attempt to write an entry into the error log and enter a loop cycle to exercise
signal lines to help in debugging the circuit. The error log is stored in the nonvolatile section of the SRAM so
that it is not destroyed during Power On Diagnostics. A signal error log entry is made each time the MC-1 is
powered up, a diagnostic test is executed, and a failure encountered.
E1 Z80 CPU Test
This test verifies operation of the internal Z80 registers. The test requires that the address, data and control
busses from the Z80 and the EPROM be operational. After disserting interrupts and sending the test
number to the front panel LEDs, the Z80 attempts to pass the values FFh, 55h, AAh, and 00h through the
Z80's internal registers. If a failure occurs the test will attempt to enter a loop to exercise the address, data
and control lines. If the MC-1 is successful in getting into a test loop, there will be a short periodic pulse on
the Serial Debug Port. The pulse can be viewed at the test port, J24 pin 1, or at U74 pin 4.
If any of the busses have serious problems or if the Z80 and/or EPROM is defective the unit will not boot
and will not be able to get into any test loop.
E2 EPROM Checksum Test
This test verifies the EPROM has the correct program by adding up all the values in the EPROM. The test
also verifies the 4 separate banks and the bank switching of the MC-1. First, the data in each of the 4 banks
of the EPROM is added up. The checksum of each bank is reported to the Serial Debug Port. This performs
an addition of the entire EPROM. The test verifies that the calculated checksum matches the checksum
value stored in the EPROM.
E3 Z80 SRAM Test
This test performs a non-destructive and destructive test on the SRAM. In the non-destructive test, it first
saves the data in the location being tested. Then writing and reading a FFh and then 00h tests that location.
The original data is then returned to the SRAM and the next location tested.
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