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LG 42LE4500 - Block Diagram

LG 42LE4500
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- 14-
LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
BLCOK DIAGRAM
BCM3556
(IC100)
BCM3556
BCM3556
(IC100)
(IC100)
TU2701
TUNER
(HORIZONTAL)
TU2701
TU2701
TUNER
TUNER
(
(
HORIZONTAL
HORIZONTAL
)
)
1 : RF_SWITCH_CTL1 : RF_SWITCH_CTL
Pull-up can’t be applied
because of MODEL_OPT_2
1 : FE_BOOSTER_CTL1 : FE_BOOSTER_CTL
The pull-up/down of LNA2_CTL
is depended on MODLE_OPT_1.
GPIO must be added for FE_BOOSTER_CTL
2 : +SCL0/SDA0_3.3V ( +3.3v normal pull up) 2 : +SCL0/SDA0_3.3V ( +3.3v normal pull up)
1 : TU_SIF +5v TU 1 : TU_SIF +5v TU
1 : TU_CVBS +5v TU 1 : TU_CVBS +5v TU
1 :TUNER_RESET +3.3V TU1 :TUNER_RESET +3.3V TU
SIF
Video
CI Slot
10067972-000LF
P4500
CI Slot
CI Slot
10067972
10067972
-
-
000LF
000LF
P4500
P4500
MC74LCX541DTR2G
IC4500
CI_CTL_BUFFER
MC74LCX541DTR2G
MC74LCX541DTR2G
IC4500
IC4500
CI_CTL_BUFFER
CI_CTL_BUFFER
11:CI_OUTCLK,CI_OUTDATA[07],
CI_OUTSTART,CI_OUTVALID
15:CI_A[0-14]…
8:/CI_D[0-7]
High chassis
Tuner +5V normal +5V TU +3.3V,+2.5V,+1.2VTuner +5V normal +5V TU +3.3V,+2.5V,+1.2V
2 : +SCL2/SDA2_3.3V (+3.3v normal pull up) 2 : +SCL2/SDA2_3.3V (+3.3v normal pull up)
4: TS_SYNC, VAL_ ERR, TS_DATA_CLK/ FE_ TS_SERIAL
TS_SYNC, VAL_ ERR, TS_DATA_CLKTS_SYNC, VAL_ ERR, TS_DATA_CLK
ss
8:FE_TS_DATA[0-3]8:FE_TS_DATA[0-3]
PP
AR4519AR4519
AR4509AR4509
AR4516AR4516
8:FE_TS_DATA[4-7]8:FE_TS_DATA[4-7]
74LVC245A
IC4501
CI_DATA_BUFFER
74LVC245A
74LVC245A
IC4501
IC4501
CI_DATA_BUFFER
CI_DATA_BUFFER
6:/CI_SEL,EBI_CS,NAND_WEb,EBI
_WE, NAND_REb, NAND_ALE
6:/CI_CE1/CE26:/CI_CE1/CE2
2
:/EBI_CS/RW
2
:/EBI_CS/RW
8:/
NAND_DATA[0-7]
8:/
NAND_DATA[0-7]
NAND FLASH
(4Gbit, 512Mb
IC101)
NAND FLASH
NAND FLASH
(4Gbit, 512Mb
(4Gbit, 512Mb
IC101)
IC101)
3:/NAND_RBb/CEb/CLE3:/NAND_RBb/CEb/CLE
LVDS
(connect to moudule)
URSA3(L.D)
IC9001
URSA3(L.D)
URSA3(L.D)
IC9001
IC9001
24:LVDS_CLK/DATA
DDR3
(1G, IC8900)
DDR
DDR
3
3
(1G, IC
(1G, IC
8900
8900
)
)
13
:/FRC_A[0-12]
13
:/FRC_A[0-12]
13
:/DDR3_A[0-12]
13
:/DDR3_A[0-12]
17
:/FRC_BA0…
17
:/FRC_BA0… 17:/DDR3_BA0…17:/DDR3_BA0…
16:/FRC_DQL/U[0-7]16:/FRC_DQL/U[0-7]
16:/DDR3_DQL/U[0-7]16:/DDR3_DQL/U[0-7]
2: URSA3_SCL/SDA
14: RXA~Bx+/-, CLK1~5
14: RXC~Dx+/-, CLK1~5
LEVEL Shift Block
IC9101
(MAX17119DS)
LEVEL Shift Block
LEVEL Shift Block
IC9101
IC9101
(
(
MAX17119DS
MAX17119DS
)
)
4: POL SOE H_CONV GVST_I/GSP(L+R)
VGI_N: from VGH +25V
VGI_P: from VGL -5V
10: VST VDD_ EVEN
VDD_ODD
CLK:/1-6
9: GVDD_ODD/GSC
GVDD_EVEN/GOE
GVST/GSP
GCLK:/1-6
Serial Flash
IC9000
Serial Flash
Serial Flash
IC9000
IC9000
4 :/ FRC_SPI_CK/DI/CZ/DO 4 :/ FRC_SPI_CK/DI/CZ/DO
P
P
-
-
GAMMA Block
GAMMA Block
IC9100
IC9100
MAX9668ETP+
MAX9668ETP+
2:/SDA3/SCL3_3.3V2:/SDA3/SCL3_3.3V
14:GMA1/3/4/6/7/9/10/12/13/15/16/18, VCOMR/VCOML
2: VCOMRFB, VCOMLFB
HVDD Block
HVDD Block
IC9102
IC9102
TPS62110RSAR
TPS62110RSAR
POWER Block
POWER Block
IC9103
IC9103
MAX17113ETL+
MAX17113ETL+
VDD_LCM(+16V)
VCC_LCM(+3.3V)
VGL(-5V)
VGH(+25V)
HVDD
PANEL_VCC
L/D except 32/37
LD650 Model
L/D except 32/37
LD650 Model

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