LG 49UJ634V - System Block Diagrams; K3 Lp Chipset and Interface Diagrams

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Only training and service purposes.
Realtek
K3Lp
DDR3 2133 X 32
(512MB X 2EA)
Hynix 20nm
DDR3 2133 X 32
(512MB X 2EA)
eMMC (4GB) Toshiba 15nm
CI Slot
B-CAS (JAPAN)
B-CAS controller
SMARTCARD_I/F
USB2 (2.0)
OCP
USB3 (2.0)
HDMI3 HDMI2(ARC)
HDMI1
Air/ Cable
DVB-S
LNB
(DT1805)
REAR(H)
P_TS_OUT
P_TS_IN
Sub Micom (RENESAS R5F100GEAFB)
X_TAL 32.768KHz
I2C 1
USB_WIFI
X_TAL 27MHz
Sub Assy
LAN
ETHERNET
SPDIF
A
V/COMP
CVBS/YPbPr
SPDIF OUT
H/P
AMP
RS-232
MAX323
MAIN Audio AMP
(DTA2010M)
I2S Out I2C 4
Vx1 51P (8 lane) : LGD 60/65/70/75
Vx1 / EPI
I2C 6
EPI PMIC (SW50B3A)
Level shifter
M0 M1
B-CAS
I2C 6
NVRAM (256Kb)
I2C 4
I2C 2
EPI block
HDMI4 (EEPROM)
K3L only. (K3Lp 256MB x 2ea SoC )
USB1 (3.0)
OCP
K3L only
IR / KEY(1Key) LOGO LIGHT(Ready)
WIFI/BT Combo MTK IC
HDMI 6G 4
EPI 60Px2 (3G, 6 lane) : LGD 43/49/55 CEDS 68Px2 (1.5G, 12 lane) : BOE
T2/C/S2 NIM tuner
TS
TS
RF IC
Demode
(T/C/S/T2/S2)
BLOCK DIAGRAM
1. K3Lp Block Diagram (External)