LG 49UJ634V - Page 14

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Only training and service purposes.
K3Lp
CEDS/EPI 6Lane 68pin
HTPDAn_IN
[GPIO_5_VBY_LOCK/EPLOCK]
[GPIO_4_VBY_HTPD/TCON_14]
BOE Panel
3840x2160@60p
1.5Gbps
[EPI_TX12~EPI_TX23]
H
T
P
D
A
IN
LOCKAn_IN
CEDS/EPI 6Lane 68Pin
LGD Panel
3840x2160@60p
3Gbps
PMIC
&
Level Shifter
SW50B3A(LGD)
SW5253(BOE)
CLK(x10)
VCOM1
VCOMLFB / VCOMRFB
VCOM2
VGL1
VST
GIP_RST
LS_VGL
VGH_EVEN
VGH_ODD
HVDD
EPI 3Lane 60P EPI 3Lane 60P
H
V
D
D
H
V
D
D
GMA
(1, 5, 6, 9, 10, 13, 24,18)
[GPIO_5_VBY_LOCK/EPLOCK]
PMIC_RESET
[GPIO7_PMIC_RESET]
LOCKOUT12
GST, E/O, MCLK, GLCK
[GPIO019_DAC_OUT]
[GPIO_0_DAC_SCLK]
[GPIO_4_VBY_HTPD/TCON_14]
[GPO_1_TCON_I2C_EN/TCON_2]
Boost/Buck
(RT5043A)
VDD, VCORE
SWG SWO
SWI
[EPI_TX12~EPI_TX23]
GAMMA
(RT6508)
BOE Only
GMA
(2, 3, 4, 7, 8,
11, 12, 15, 16, 17)
[GPIO_2_TCON_SCL/TCON_9]
[GPIO_1_TCON_SDA/TCON_5]
68pin
60pin
68pin
60pin
3. EPI / CEDS Block Diagram