LG 49UJ634V - Page 22

- 22 -
Copyright © LG Electronics Inc. All rights reserved.
Only training and service purposes.
K3Lp
K3L_DDR_0_ADDR_[0:14]
DC1_A [0:14]
K3L_DDR_0_CON_BA[ 0:2]
DC1_BA [0:2]
K3L_DDR_0_CLK_ P/N K3L_DDR_0_CON_CKE K3L_DDR_0_CON_ODT
DC1_ODT
K3L_DDR_0_CON_RA SN /CASN
DC1_RAS / CAS
K3L_DDR_0_CON_WEN
DC1_WE
K3L_DDR_0_DQS_0_P/N
K3L_DDR_0_DQS_1_P/N
DC1_DQS0 / DQS0B
DC1_DQS1 / DQS1B
DC1_DQS2 / DQS2B DC1_DQS3 / DQS3B
K3L_DDR_0_DQ [0:15]
K3L_DDR_0_DQ [16:31]
DC1_DQ [0:15]
DC1_CLK / CLKB
DC1_CKE
A[0:14]
BA[0:2]
ODT
RAS/CAS
WEN LDQS/~LDQS
DDR3 IC400
CK / ~CK
CKE
UDQS/~UDQS
DC1_DQ [16:31]
DQ[0:15]
A[0:14]
BA[0:2]
ODT
RAS/CAS
WEN
DDR3 IC401
LDQS/~LDQS
CK / ~CK
CKE
UDQS/~UDQS
DQ[0:15]
K3L_DDR_0_DQS_2_P/N
K3L_DDR_0_DQS_3_P/N
1k ohm
DC1_CSB
K3L_DDR_0_CON_CS 0
~CS
~CS DC1_CSB_1
K3L_DDR_0_CON_CS 1
11. DDR Block