LG 50PC5D - Page 12

Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
BLOCK DIAGRAM
Signal path for CVBS, Component, RGB
Comp1_Y
H Sync
V Sync
BCM3553
Comp1_Pb
Comp1_Pr
74F08D
Component 1
Input
Component 2
Input
RGB Input
RGB H_Sync
Side AV CVBS Rear AV
Rear S_Video Y/C
Side S_Video
Y/C
CVBS
CVBS 2
L1/C1
CVBS 3
L2/C2
ANT/ Cable
TUNER
IF_P
IF_N
IF_P from TUNER for DTV
IF_N from TUNER for DTV
CVBS 1
EEPROM
FOR EDID
DDC SDA DDC SCL
RGB V_Sync
LVDS_Tx
Out
Only for HD
Component_1 S/W Component_2 S/W Rear_CVBS_ S/W
RGB S/W
GPIO[0:6]
Comp2_Y Comp2_Pb
Comp2_Pr RGB_G RGB_B RGB_R
DDC SCL to Micom
for Download
LPF 6 Mhz
LPF 30Mhz LPF 30Mhz LPF 30Mhz LPF 30Mhz LPF 30Mhz
LPF 30Mhz
LPF 6 Mhz
LPF 6 Mhz
LPF 6 Mhz
DDC SDA to Micom
for Download
DVO Out[0:29]
Rear_S-Video_ S/W Side_CVBS_ S/W
Side_S-Video_ S/W
31p
LVDS
Con.
31p
LVDS
Con.