LG 60PZ550 - Page 35

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Block Diagram – 3DF Block Diagram
I2C
L/R DETECT
3DF_ASIC RESET
LVDS 2Ch
DDR2
(256Mbit)
3D :
1920x1080/60Hz
(S/S, T/B, C/B, F/S)
1920x1080/48Hz
(F/S)
X-tal
(25MHz)
Serial_Flash
(2Mbit)
LVDS 2Ch
Left (2D):
1920x1080/60Hz
LVDS ( 80Pin )
LVDS 2Ch
3D_SYNC_OUT
■ Processing
 LVDS-Rx , Dual Link 10 bit (25~85MHz)
 LVDS-Tx , Quad Link 10 bit (25~85MHz)
 DDR2-PHY : 333MHz (Max.350MHz)
(DDR2 x16 1ea, 512Mb/256Mb)
 GPIO#32
BCM3549_XSP
(3D_PIP)
BCM3549_XSP
(3D_PIP)
3DF_ASIC
LG8300
3DF_ASIC
LG8300
PDP
PDP
3D_SYNC
EMITTER_PULSE
Right :
1920x1080/60Hz
1920x1080
60Hz
PO_RST_N
GPIO[2]
I2C
I2C_M
RF_Tx
RF_Tx
RF_Shutter_Glasses
3D_GPIO
3