LG 60UM7100DUA - System Architecture Overview

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Only for training and service purposes.
BLOCK DIAGRAM
Main IC
eMMC (4GB)
USB1 (2.0)
OCP
USB2 (2.0)
HDMI3 HDMI2(ARC) HDMI1
Air / Cable
TUNER
CVBS SIF
MICOM
IR / KEY
USB_WIFI
X_TAL
27MHz
Sub Assy
LAN
ETHERNET
SPDIF
AV/COMP
CVBS/YPbPr
SPDIF OUT
MAIN Audio AMP
I2S Out I2C 4
Vx1 51P (8 lane)
Vx1 / EPI/ CEDS FCIC SPI/ I2C 6
Main
PMIC
M0
M1
IF
CVBS/SIF
GST/MCLK/GCLK/EO/I2C 6
NVRAM (256Kb)
I2C_1
I2C 2
EPI/CEDS block
TS
DDR3 2133 X 32 (256MB X 2EA)
DDR3 2133 X 32
(512MB X 2EA)
EPI 60P (65”:8 lane, 55”↓:6lane), CEDS 68P
IR/KEY
I2C_SDA_1
1.5V
DDR
0.95V
Core&CPU
3.3V
Normal
1.0V
Eth
3.5V
ST_BY
1.8V
5V
Normal
Sub
PMIC
0.95V 1.5V
3.3V 5V
1V
1.8V
3.5V_ST
0.95V 1.5V
3
.3V
3.3V
5V
1V
1
.8V
1.8V
3.5V_ST
3.5V_ST
3.3V
3.5V_ST
3.5V_ST
13V
3.5V_ST
13V
3.5V_ST
13V
3.3V
13V
13V
3.3V
13V(PANEL_VCC)
13V(PANEL_VCC)
To
P
anel
From
Power
B/D
13V
To WIFI/BT
C
ombo
IF+/-
Gamma
IC
3.3V
Signal Flow
Supply Power
Input/Output Power