LG 65UF9500 - Page 85

H15
14. DDR(LM, GM) Block
M0_DDR_A[0:15]
M0_DDR_A[0:15]
M0_DDR_A0 [0:15]
M0_DDR_BA[0:2]
M0_DDR_BA[0:2]
M0_DDR_BA [0:2]
M0_D_CLK/N
M0_U_CLK/N
M0_DDR_CKE
M0_DDR_CKE
M0_DDR_ODT
M0_DDR_ODT
M0_DDR_ODT
M0_DDR_RAS/CAS
M0_DDR_RAS/CAS
M0_DDR_RASN / CASN
M0_DDR_WEN
M0_DDR_WEN
M0_DDR_WEN
M0_RET
M0_DDR_DQS0/N0
M0_DDR_DQS1/N0
M0_DDR_DQS0 / DQS_N 0
M0_DDR_DQS0 / DQS_N 1
M0_DDR_DQS0 / DQS_N 2
M0_DDR_DQS0 / DQS_N 3
M0_DDR_DQ [0:15]
M0_DDR_DQ [16:31]
M0_DDR_DQ [0:31]
M0_DDR_U_CLK / CLKN
M0_DDR_CKE
M0_DDR_D_CLK / CLKN
A[0:15]
BA[0:2]
CKE
ODT
RASN/CASN
WEN
DQSL / ~DQSL
DDR3 IC500
DQSU / ~DQSU
CK / ~CK
A[0:15]
BA[0:2]
CKE
ODT
WEN
RASN/CASN
DDR3 IC502
CK / ~CK
DQSL / ~DQSL
DQSU / ~DQSU
M0_DDR_DQS2/N2
M0_DDR_DQS3/N3
MICOM
H15
M1_DDR_A[0:15]
M1_DDR_A[0:15]
M1_DDR_A0 [0:15]
M1_DDR_BA[0:2]
M1_DDR_BA[0:2]
M1_DDR_BA [0:2]
M1_D_CLK/N
M1_U_CLK/N
M1_DDR_CKE
M1_DDR_CKE
M1_DDR_ODT
M1_DDR_ODT
M1_DDR_ODT
M1_DDR_RAS/CAS
M1_DDR_RAS/CAS
M1_DDR_RASN / CASN
M1_DDR_WEN
M1_DDR_WEN
M1_DDR_WEN
M1_RET
M1_DDR_DQS0/N0
M1_DDR_DQS1/N0
M1_DDR_DQS0 / DQS_N 0
M1_DDR_DQS0 / DQS_N 1
M1_DDR_DQS0 / DQS_N 2
M1_DDR_DQS0 / DQS_N 3
M1_DDR_DQ [0:15]
M1_DDR_DQ [16:31]
M1_DDR_DQ [0:31]
M1_DDR_U_CLK / CLKN
M1_DDR_CKE
M1_DDR_D_CLK / CLKN
A[0:15]
BA[0:2]
CKE
ODT
RASN/CASN
WEN
DQSL / ~DQSL
DDR3 IC501
DQSU / ~DQSU
CK / ~CK
A[0:15]
BA[0:2]
CKE
ODT
WEN
RASN/CASN
DDR3 IC503
CK / ~CK
DQSL / ~DQSL
DQSU / ~DQSU
M1_DDR_DQS2/N2
M1_DDR_DQS3/N3
MICOM
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