LG 65UF9500 - Page 86

H15
15. DDR(EM) Block
M2_DDR_A[0:15]
M2_DDR_A[0:15]
M2_DDR_A0 [0:15]
M2_DDR_BA[0:2]
M2_DDR_BA[0:2]
M2_DDR_BA [0:2]
M2_D_CLK/N
M2_U_CLK/N
M2_DDR_CKE
M2_DDR_CKE
M2_DDR_ODT
M2_DDR_ODT
M2_DDR_ODT
M2_DDR_RAS/CAS
M2_DDR_RAS/CAS
M2_DDR_RASN / CASN
M2_DDR_WEN
M2_DDR_WEN
M2_DDR_WEN
M2_RET
M2_DDR_DQS0/N0
M2_DDR_DQS1/N0
M2_DDR_DQS0 / DQS_N 0
M2_DDR_DQS0 / DQS_N 1
M2_DDR_DQS0 / DQS_N 2
M02DDR_DQS0 / DQS_N 3
M2_DDR_DQ [0:15]
M2_DDR_DQ [16:31]
M2_DDR_DQ [0:31]
M2_DDR_U_CLK / CLKN
M2_DDR_CKE
M2_DDR_D_CLK / CLKN
A[0:15]
BA[0:2]
CKE
ODT
RASN/CASN
WEN
DQSL / ~DQSL
DDR3 IC600
DQSU / ~DQSU
CK / ~CK
A[0:15]
BA[0:2]
CKE
ODT
WEN
RASN/CASN
DDR3 IC602
CK / ~CK
DQSL / ~DQSL
DQSU / ~DQSU
M2_DDR_DQS2/N2
M2_DDR_DQS3/N3
MICOM
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