LG Flatron L1715S - Page 24

- 24 -
CAT24WC08J-TE13 8P
A
0
A
1
A
2
V
SS
V
CC
WP
SCL
SDA
A
0
A
1
A
2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
0
A
1
A
2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
EXTERNAL LOAD
SDA
WP
D
OUT
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
LOGIC
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SLAVE
SCL
A
0
A
1
V
CC
V
SS
A
2
ADDRESS
COMPARATORS
CONTROL
LOGIC
ACK
E PROM
2
PIN CONFIGURATION
DIP Package(p) SOIX Package(J)
TSSOP Package(U)
BLOCK DIAGRAM
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
WP
Vcc
Vss
Function
Device Adress Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to + 6.0V power Supply
Ground