LG KG290 - Page 48

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3. TECHNICAL BRIEF
• 256 Mbits NOR Flash
♦ High performance Read-While-Write/Erase
- 85 ns initial access
- 52 MHz with zero wait state, 17 ns clock-todata output synchronous-burst mode
- 25 ns asynchronous-page mode
- 4-, 8-, 16-, and continuous-word burst mode
- Programmable WAIT configuration
- Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ)
- 1.8 V low-power buffered programming at 7 µs/byte (Typ)
♦ Architecture
-Asymmetrically-blocked architecture
-Multiple 8-Mbit partitions: 64-Mbit and 128-Mbit devices
-Multiple 16-Mbit partitions: 256-Mbit devices
-Four 16-Kword parameter blocks: top or bottom configurations
-64-Kword main blocks
-Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE)
-Status register for partition and device status
♦ Power
-VCC (core) = 1.7 V - 2.0 V
-VCCQ (I/O) = 2.2 V - 3.3 V
-Standby current: 30 µA (Typ) for 256-Mbit
-4-Word synchronous read current: 16 mA (Typ) at 52 MHz
-Automatic Power Savings mode
• 64 Mbits PSRAM
♦ Device Voltage
-Core: VCC = 1.8 V (Typ)
-I/O: VCCQ = 1.8 V or 3.0 V (Typ)
♦ PSRAM Performance
-70 ns initial access, 25 ns async page read at 3.0V I/O (16-Mbit PSRAM)
-65 ns initial access, 18 ns async page reads at 3.0V I/O
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Only for training and service purposes