LG KS660 - Page 47

- 48 -
LGE Internal Use Only Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
TEKC
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VSS_4
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VSS_5
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K6
VSS_7
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VSS_8
L6
VSS_9
BTIAW
41J
41K
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EW
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VIP0DATA0
R11 P11
VIP0DATA1
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VIP0DATA2 VIP0DATA3
P10 N11
VIP0DATA4 VIP0DATA5
N10 R9
VIP0DATA6 VIP0DATA7
P9
VIP0DATA8
N9
VIP0DATA9
N8
VIP0HREF
P8 P7
VIP0VSYNC
VSS_1
G7
L7
VSS_10
J6
VSS_11
J7
VSS_12
L11
VDDR3_4 VDDR3_5
G6
F6
VDDR3_6 VDDR3_7
J5
VDDR3_8
E11
VDDR4_1
K10
VDDR4_2
L10
E9
VDDR5_1 VDDR5_2
E10
E8
VDDR6 VDDR7
N4
N15
VDDR8A VDDR8D
R13
VDD_EFUSE
N7
VIP0CLK
R12 R5
VIP0CLKO
VDDC_5
J8 J9
VDDC_6 VDDC_7
F9
F10
VDDC_8
K8
VDDC_9
L9
VDDR10 VDDR1_1
H11
VDDR1_2
J10 J11
VDDR1_3
G11
VDDR1_4
G5
VDDR2_1
F5
VDDR2_2
H5
VDDR2_3
H6
VDDR3_1
E6
VDDR3_2 VDDR3_3
K5
D
M
C0CD
S
9
A
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1QD0CDS
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2QD
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9
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0
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DS
PW
0
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DS
9
C
SLEEP
L8
SRCCLK0
R8 R7
SRCCLK1
3M
S
S
TESTEN
A7
H9
VDDC_1 VDDC_10
K9
H10
VDDC_2
G9
VDDC_3
G10
VDDC_4
E7
NC_5
R1
NC_6
4
1
L
BE
O
PVDD
R6
PVSS
P6
BT
E
SER
4
1
A
N5
RESETB_CORE
P14
RSET
7C
0SU
B
S
8B
1
S
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8
A
2
S
UBS
7
B
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SCL
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LC
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2K
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CL
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CL
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2DD
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L
2
E
3
E
3DDCL
2
H
4
D
DCL
5DDCL
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6DD
C
L
2F
1E
7
D
DC
L
8
D
DC
L
1
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9
D
DCL
2
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SL
3
L
3
1
L
RM
NC_1
R15 A1
NC_2 NC_3
A15 C3
NC_4
4
1
B
B
0
T
N
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N12
I_TESTA
E5
I_VDD_1 I_VDD_2
F11
I_VDD_3
L5
I_VDD_4
K11 J13
I_VDQT_1
K13
I_VDQT_2
3F
0
DD
C
L
1DD
C
L
3
G
0
1D
D
CL
1
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CL
1
J
21D
D
CL
3
H
31DDCL
4
1
DDCL
3
K
1
K
51D
D
CL
1
1B
5COIPG
11A
6
CO
I
PG
7COIPG
3
1A
0
DO
IP
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2R
1
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DO
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PG
1
M
3
DO
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PG
3
R
4DOIPG
1
P
5
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2
P
2M
6
DOIPG
4
P
0
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PG
1EOIPG
3P
3
N
2
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I
PG
2
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4R
4
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4
A
4
C
8
1
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I
PG
91AO
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PG
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D
2AOIPG
4
B
3AO
I
PG
1
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3
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4AOIPG
5AOIPG
1B
6
A
OI
PG
3B
1
D
7
AO
I
PG
2C
8
A
OI
PG
9AOI
P
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6C
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31C
2
1
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PG
3
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0AOIPG
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AO
I
PG
2
A
11AO
I
PG
6
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2
1AOIPG
6A
5A
3
1AOI
P
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5C
41AOIPG
51AOIPG
5B
AVSSDA
N14
AVSSDI
P13
4
1
H
0
E
B
51H
1E
B
COMP
P15
51
J
B
SC
CSI_SELECT
P12
1L
K
L
CD
31D
0Q
D
1QD
3
1
E
5
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01QD
51F
1
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D
2
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3
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5
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4
1G
4
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3
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5
1
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P_
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5
1
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91DA
2D
A
3
1
N
0
2D
A
51L
1
2
DA
5
1
M
22DA
4
1
M
AVSSBG
R14
9
5
8
C
u1.0
R819100K
60
8PT
018P
T
R815100K
FB806
1.2K R808
MMV
_2V1
_
T
X
E
EXT_2V6_IO
30
8
PT
SIM1_CLK32K
NE
_
ODL_MAC
TNI_M
M
KLCM_M
A
C
ITA_
K
LCM_M
M
)4
(
D
_
F
I
D
)5(D
_
F
I
D
)6
(
D
_
F
I
D
)
7(D
_
F
I
D
)8
(
D
_
F
I
D
)
9(D
_
F
I
D
D
C
_FI
D
D
R
_MM
TESE
R
_
M
M
MM_RESETB_CORE
CAM_SCL
CAM_SDA
MM_SLEEP
26M_TVOUT
MIPI_CLK_P
MIPI_CLK_N
MIPI_DATA_P
MIPI_DATA_N
TIAW_MM
RW_
MM
6DA_
M
M
7
D
A_M
M
8DA_
M
M
9
D
A_M
M
C
N
Y
SV_
F
I
D
S
S
A
PYB
_
F
I
D
T
C
E
T
ED_
V
T
K
L
C
_
S
2
I_MM
SW
_
S
2
I_
M
M
O
D
S
_
S
2I_M
M
0A
W
_
2
S
2
I
_
MM
XT_2S2
I
_
M
M
T
ES
ER
_M
A
C
DP
_
MAC
N
E
_
H
S
A
LF
NE_HCROT
R
W_FID
)0(D_F
I
D
)1(D
_
FID
)01(D_F
I
D
)11(D
_
FID
)21(D_F
I
D
)31(D
_
FI
D
)41(D_F
I
D
)51(D
_
F
I
D
TES
E
R_
F
ID_MM
SC_FID
)
2
(
D
_FID
)
3
(
D
_FI
D
6
1
A_M
M
0
SC_
M
M
DR_
F
I
D
0D
A
_
M
M
1
DA
_
MM
0
1
D
A_M
M
1
1DA_
M
M
2
1
D
A
_M
M
3
1DA_
M
M
41DA_
M
M
51
D
A_M
M
2D
A
_
M
M
3DA_MM
4
DA
_M
M
5DA_MM
< Fig 24. 5M MIPI Interface & Companion IC Circuit Diagram >