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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
R4110 0
DNI
R4103
PM8110
U4100
105
97
108
54
48
3
42
19
60
68
91
82
100
93
34
26
11
2
62
47
20
46
28
41
71
76
57
92
101
84
88
89
81
90
GPIO_01/RFCLK1_EN
GPIO_02/RFCLK2_EN
GPIO_03/Ext_5VBOOST_EN
GPIO_04/BATT_UIM_ALRM
PS_HOLD
KPD_PWR_N
PON_RESET_N
RESIN_N
SPMI_CLK
SPMI_DATA
RF_CLK1
RF_CLK2
BB_CLK_EN
BB_CLK
XO_THERM
GND_XOADC
XTAL_19M_IN
XTAL_19M_OUT
REF_BYP
GND_REF
VREF_LPDDR
HW_ID
MPP_01/VREF_PADS
MPP_02/HR_LED_SNK
MPP_03/WLED_CTL
MPP_04/PA_THERM
VREG_XO
GND_XO
VREG_RFCLK
GND_RF
SLEEP_CLK
VREF_BAT_THM
BAT_THERM
BAT_ID
C41050.1u
R4106 0
R4109 0
C4300
1u
R4100
200K
TOL=0.01
C4106 0.1u
TP4101
+1V8_VREG_L8
1RAA19200AAA
19.2MHz
X4100
SENSOR
4
XTAL2
3
XTAL1
1
GND1
2
DNI
C4109
1uC4108
VREF_LPDDR2
1uC4107
DNIC4101
10KR4102
+1V8_VREG_L8
100K
R4107
C4102 1n
DNI
C4104
C4103
DNI
TP4105
U4300 RT9718L
VIN1
1
VOUT2
8
VIN2
2
VOUT1
7
OVPFB
3
GND
6
WRN
4
EN
5
PGND
9
VBUS_USB_OVP_IN VBUS_USB_IN
TP4106
R4101
100K
DNI
C4100
+1V8_VREG_L8
PA_THERM_0WTR0_XO_IN
BB_CLK
MSM_PS_HOLD
PMIC_SPMI_CLK
PMIC_SPMI_DATA
BATT_UIM_ALARM
VREF_MSM_PX_MPP_1
VREF_BAT_THERM
JTAG_PS_HOLD
SLEEP_CLK
MSM_RESIN_N
PM_USB_ID
KYPD_PWR_N
BB_CLK_EN
WCN_TCXO_IN
VBAT_THERM
PCB_REVISION
PCB_REVISION
Rev.D
0830_Change
Remove R4104(QMC)
Rev.D
0902_Change
0902_Change
Rev.D
Rev.C
Long Key Reset
REV.0.5
0.6125
<4-1-4-1_PMIC_PM8110_DATA>
CAD Note: Route these signals close together
without any other connections to intermediate GND fills.
C4105 GND must connect (via) directly to the main GND
Note 2: REF_GND must connect (via) directly to C4105;
to the GND plane of the (-) side of C4102.
C4102 and x4100 THRMST/GND that connects
Note 1: Implement a GND island for PM8110 XOADC_GND,
Note 1
GND Island
Note 2
<4-3-2_OVP_RT9718L>
REV.0.4
68K
43K
30K
20K
100K
100K
100K
100K
C
B
0.000
1.800
0.900
A
0
100K
DNI
100K
1.0
1.1
E
D
100K
100K
DNI
0.541
0.729
0.415
0.300
PCB REVISION
0624_change
5%
5%
Rev.1.0
0801_change
100K 180K
1.157
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