3. TECHNICAL BRIEF
3.8.8 Mode Select and JTAG Interfaces
The MSM8x55 IC JTAG interface conforms to the IEEE 1149.1A-1003 standard specifying components that accept
test instruction and data inputs, then provide the respective results as outputs in a serial format. The standard
requries a test access port and a boundary-scan architecture to fulfill these requirements
T This test circuitry is used for board-level testing, and confirms the following:
T That each component on the board performs its function correctly
T That all components are interconnected in the correct manner
That the entire design begaves as intended These confirmations are achieved using a boundary-scan
architecture that includes a shift register stage (or cell) adjacent to each component pin so that signals at the
component's boundaries can be tested, controlled,and observed. The boundary-scan cells are connected serially
as a long chain, and behave as an overall shift register.
3.8.9 General-Purpose Input/Output Interface
This device has a number of general-purpose programmable input/outputs (GPIO). These inputs and ouputs
need to be protected form non-secure master, CPUs, and processes. Secure access privileges for the GPIOs are
always controlled by the root-of-trust processor. This may include programming the pull-up/pull/down/keeper
usage, the drive strength, and any alternate hardware use of each pad.
Specifically the non-trusted masters must be prevented from reconfiguring GPIO channels to:
T ensure critical GPIOs/channels are not disabled.
T ensure that non-secure observation of secure GPIOs does not occur.
T ensure that non-secure observation of interrupts associated with secure GPIOs does not occur.
T ensure that when Scorpion is the root-of-trust processor, the MPROC maintains a region of GPIOs
unobservable/inaccessible to other non-root-of-trust masters.
T ensure the alternative function, intended be used only under certain specific circumstances is not
selected with malicious intent.
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