LG LG-V909DW - Star Tablet: System Clock & Reset

6. BLOCK DIAGRAM
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Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
LGE Internal Use Only
LDO
BU28TD2WNVX
EUSY0407101
T20
PMIC
TPS658621AZGUR
CP
MDM6200
BT/WiFi/FM
SWB-B25
SMZY0025001
PMIC
PM8028
X-Tal : 32.768Khz
X-Tal : 12Mhz
XI
XO
PWR_I2C_SCL PWR_I2C_SDA
TCXO_EN
XO
SO_SUP
XTAL1
XTAL2
TCLK2
SLEEP_CLK
OSCIN
PWR_INT_N
TCXO
38.4Mhz
CLK_32K_IN
CORE_PWR_REQ CPU_PWR_REQ
SCLK
SDAT
INT_N
SM0EN SM1EN
nONKEY
SYS_RESET_N
NOPOWER_N
TCLKAP
TCXO
19.2Mhz
AFC_DAC
GPIO_PV3
GPIO_PV0
GPIO_PV1
Wakeup pad
KPD_PWR_N
GPIO_1
X
0
CLK_32K_OUT
CLK_REQ
vcc
STBY
VOUT
VBAT
VIN
MDM_RESET_FLAG_N
MDM_RESET_1.8V
Star Tablet : System Clock & Reset
X-Tal : 32.768Khz
MDM_PWRON_1.8V
RESIN_N
XO_RF
MDM_RF_TCXO
XO_OUT_A0
XO_OUT_D1
MDM_TCXO
SYS_CLK
SLEEP_CLK0
XO_OUT_D1_EN
XO_OUT_D1_EN
MDM_SLEEP_CLK
SLEEP_CLK
Star Tablet : System Clock & Reset