DMPi Series
LSIS Co.,Ltd. 23
Note1)
Overcurrent delay time setting
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
Note1) (OFF 0.1A)
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N
R
C
50%
120%
A
%
S
T
N