Marantz CDA-94 - Page 5

2. DESCRIPTION OF CIRCUIT OPERATION
1.1 Input Circuit
Q301 is a circuit which amplifies the 0.5Vp-p digital signal
to the 5Vp-p TTL level and performs waveform shaping.
Amplification is performed in the first stage, in which the
signal is amplified to approximately 4Vp-p.
The invertors in the second and third stages perform
waveform shaping, after which the signal is sent to the
input selector circuit.
203 Q2ol e201
(t76) (2/6) {3/6)
0203 through 0205 form an input selector circuit with a
NAND gate, and the circuit to which the 5V control
voltage has been. applied from the front board function
switch (SSO1) and monitor switch (SSO2) is sent to the
demodulator circuit in the next stage. At the same time,
the selected source signal is output from the TAPE OUT
terminal.
1.2 Demodulator and PLL Circuit
The demodulator and PLL block consists of 0301, 0303,
0351, and 0352 through 0354. This block has a variable
resistor and is adjusted as follows: ;
After applying a signal to the input-and turning R351 fully
counterclockwise, turn it back gradually clockwise until
the PLL locks (approximately 5 — 20 degrees). Next
observe the 0301 pin 6 and pin 8 waveform with a two-
channel synchro and readjust for 1 : 2 as shown in the
diagram.
7 ae
NOTE: Perform this adjustment with a sampling frequen-
cy of 48 kHz, and check that it locks at 44.1 kHz
and 32 kHz.
0352 through 0354 cut the high frequency component of
the DC voltage in accordance with the phase changes from
the phase comparator (pin 6, pin 8) in Q301, the PLL low
pass filter, and supply the DC voltage to the Q351 VCO
which follows.
0303 is a pulse generator of approximately 330 Hz. When
unlocked, it oscillates the VCO control voltage over a wide
range, and when the input signal is input, it generates the
discharge output to lock the PLL. 0355 is the switching
FET for this purpose. D360 through D365 form the varis-
tor for temperature compensation.
1.3 Digital Filter Block
The three signals output from 0301 (DATA, BCK, LRCK)
are sent to the 0302 digital filter in the following stage,
converted into frequencies 4 times higher, then output.
However, the reading timing of the Q302 data starts with
a delay of one block, so data is delayed by one block by
0304 then sent to 0302.
When the PLL is unlocked, the clock for operating Q302
is oscillated, so the O302 output data is oscillated, genera-
ting noise in the audio output. In order to prevent this, the
clock is cut with the Q305 NAND gate switch when un-
locked.
1.4 Photocoupler Block
Q371 through Q374 form a photocoupler which performs
isolation when connecting the three outputs from the
digital filter and the emphasis contro! signals to the audio
circuitry in the following stage.
1.5 Sampling Frequency Display Block
Q310 and 0311 convert the LRCK pulse waveform into a
saw tooth waveform and obtain a peak value in accordance
with the sampling frequency. Q306 is a comparator, 1/2
judging for 44.1 kHz and 48 kHz, 2/2 judging for 32 kHz.
With 44.1 kHz and 48 kHz, the difference in the peak
values is of approximately 0.6V. In order to prevent er-
roneous display, the comparator 1/2 reference voltage is
adjusted as follows with R308. ;
3 PIN t
O.IV
Q306 [ 4 4 i
2 PiN ov
Apply a sampling frequency 48 kHz signal, observe the
0306 pin 3 and pin 2 waveforms, and adjust R308 so
that the difference in voltage between the two is 0.1V.
For the comparator’s two outputs, the sampling display
driver transistor is driven by the Q308 and Q309 logic
operation circuit. The logic operation circuit is a circuit
for displaying one of the frequencies even if there is no
input. Furthermore, for the comparator output, approxi-
mately 0.5 seconds are required from when the input signal
is applied until operation becomes normal, so the display
circuit is not operated when unlocked and for approximate-
ly 1 second after locked using 0315 through 0317.
The 0312 32 kHz display driver is also used as the audio
circuit 15 kHz low pass filter on/off relay driver.
MZ 1763