MDR-2000
V3
User's Reference Manual
Hardware
Chapter 7
HARDWARE
The purpose
of
this section
is
to describe the functional components
of
the MDR-2000 hardware.
As well a description
of
the cable requirements is provided.
7.1 Hardware Overview
The MDR-2000 is a Z80 CPU based system with 64K bytes
of
processor memory (RAM) and
128K to 8MB
of
buffer memory. There are two RS232-C serial ports each capable
of
transmitting
and receiving at speeds from 300 Baud to 19200 Baud.
In
addition, there is provision for a 128K-bit ROM, which overlays the first 16K
of
processor
memory.
Clock interrupts are available on the MDR-2000 and are used to drive certain housekeeping
routines such as the internal timestamp and interval timers. Output
is
driven on a polled basis, and
input
is
interrupt driven through vector 38H.
An
additional keepalive circuit is provided which generates an interrupt at vector 66H
if
it
is
not
reset by the software. In the event
of
a hardware or software malfunction this feature would assure
that the MDR-2000 was restarted automatically. The reset
is
performed by directing a single byte
of
output to the appropriate I/O address.
The MDR-2000 requires a single l lOVAC outlet to supply its internal power supply. This power
supply is used to provide the requirements for the MDR-2000 as well as keep its battery backup
fully charged. In the event
of
a power disruption, the MDR-2000 has sufficient battery capacity for
about 60 minutes
of
operation.
The unit
is
housed in a single cabinet and requires no cooling fans or external climate except for
that found in the normal office or communications room environment.
7-1
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