2.3
Pin Functions
(cont.)
While interfacing to a processor other than the CP1600 would simply
require simulating the above decoding, the redundancies in the PSG
functions vs. bus control signals can be used to advantage in that
only four of the eight possibledecoded bus functions are required by
the PSG. This could simplify the programming of the bus control
signals to the following, which would only require that the processor
generate two bus control signals (BDIR and BCl, with BC2 tied to
+5v):
Each of these signals is the output of its corresponding D/A
Converter, and provides an up to 1V peak-peak signal representing
the complex sound waveshape generated by the PSG.
IOA7--IOAO (input/output): pins 14--21 (AY-3-8910)
pins 7--14 (AY-3-8912)
IOB7--1OB0 (input/output): pins 6--13 (AY-3-8910)
(not provided on AY-3-8912)
Input/Output A7-- AO, B7-- B0
Each of these two parallel input/output ports provides 8 bits of
parallel data to/from the PSG/CPU bus from/to any external devices
connected to the IOA or IOB pins. Each pin is provided with an on-
chip pull-up resistor, so that when in the “input” mode, all pins will
read normally high. Therefore, the recommended method for scan-
ning external switches, for example, would be to ground the input bit.
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