.
TEST 1:
pin 39 (AY-3-8910)
pin 2 (AY-3-8912)
TEST
2: pin 26 (AY-3-8910)
(not connected on AY-3-8912)
These pins are for GI test purposes only and should be left open-&
not use as tie-points.
Vcc:
pin 40 (AY-3-8910)
pin 3 (AY-3-8912)
Nominal +5Volt power supply to the PSG.
Vss:
pin 1 (AY-3-8910)
pin 6 (AY-3-8912)
Ground reference for the PSG.
2.4 Since the PSG functions are controlled by commands from the
Bus Timing
system processor, the common data/address bus (DA7--DAO) re-
quires definition as to its function at any particular time. This is
accomplished by the processor issuing bus control signals, previ-
ously described, defining the state of the bus; the PSG then decodes
these signals to perform the requested task.
The conditioning of these bus control signals by the processor is the
same as if the processor were interacting with RAM: (1) the processor
outputs a memory address; and (2) the processor either outputs or
inputs data to/from the memory. The “memory” in this case is the
PSG’s array of 16 read/write control registers.
The timing relationships in issuing the bus control signals relative to
the data or address signals on the bus are reviewed in general in the
following section, and in detail in Section 7, Electrical Specifications.
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