Minebea CSD-891B - Page 158

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(3) When ERROR is occurred
DATA
POL.
P.C.
ON
ERROR
ON
ONON ON ONON
 ● At the time of ERROR output, output transistor at ERROR signal
will become ON(Negative logic electrically). Moreover, for each DATA,
POL., all of the output transistor will become OFF at the time of
ERROR output(Positive logic electrically).
(4) When the HOLD signal is input
4 times/s：Approx. 250 ms at max.＋Input response time
20 times/s：Approx. 50 ms at max.＋Input response time
DATA
POL
P.C.
HOLD
ON
50 times/s：Approx.20 ms at max.＋Input response time
100 times/s：Approx.10 ms at max.＋Input response time
4 times/s：Approx.250 ms at max.＋Input response time
20 times/s：Approx.50 ms at max.＋Input response time
50 times/s：Approx.20 ms at max.＋Input response time
100 times/s：Approx.10 ms at max.＋Input response time
200 times/s：Approx.5 ms at max.＋Input response time 200 times/s：Approx.5 ms at max.＋Input response time
 ● At the time of HOLD signal input, output transistor for the P.C. will
be OFF condition. (Positive logic electrically.)
● After inputting the HOLD signal, it takes the following response
times to freeze the DATA, POL or cancellation of HOLD is executed.
At 200 times/s：Approx.5 ms at maximum＋Input response time
At 100 times/s：Approx.10 ms at maximum＋Input response time
At 50 times/s：Approx.20 ms at maximum＋Input response time
At 20 times/s：Approx.50 ms at maximum＋Input response time
At 4 times/s：Approx.250 ms at maximum＋Input response time
9−2−6. Output condition
Setting
output
logic
Output
data
Condition of
Pin−COM level
a
t
the
time
of
voltage
S
ett
i
n
g
output
l
og
i
c
O
utput
d
at
a
Condition
of
transistor
a
tt
he
time o
f
vo
l
tage
supply externally.
Negative
logic
Yes ON L
N
egat
i
ve
l
og
i
c
No OFF H
P
ositive
logic
Yes OFF H
P
os
i
t
i
ve
l
og
i
c
No ON L