8
1 FRAME SPECIFICATIONS
1.1 MODBUS Protocol Frame Specifications
*1 The least significant bit from the previous exclusive OR (XOR)
Data is stored as follows:
ASCII mode
In this mode, frames are received or sent in units of 2 characters (2 bytes) in ASCII codes.
The frame specifications are compliant with the MODBUS protocol specifications.
Error check in ASCII mode
The error check in the ASCII mode is conducted by LRC (Longitudinal Redundancy Check).
C24 calculates the LRC by the following steps.
Follow the same steps to calculate the LRC when conducting an error check on the target device.
1. To calculate the LRC, convert the ASCII codes within the error check range into the RTU format (binary).
2. Add the figures in units of contiguous 8 bits in the frame. (Excluding carries during addition.)
3. Change the result of step 2 to a 2's complement. (Reverse the bits and add 01H.)
4. Convert the result of step 3 to an ASCII code.
The following are calculation examples in the case where function code 01H is sent to station No.2.
Error check range of the request message is as follows:
• Address field (1 byte): 02H
• Function code (1 byte): 01H
7 Shift by 1 bit to the right. Shift 1 0100 0000 1001 1100 1
Since the flag is '1', calculate the exclusive OR (XOR) from the
result in 'Shift 1' and generator polynomial (A001H).
Generator polynomial (A001H) 1010 0000 0000 0001
Exclusive OR (XOR) 1110 0000 1001 1101
Shift by 1 bit to the right. Shift 2 0111 0000 0100 1110 1
Since the flag is '1', calculate the exclusive OR (XOR) from the
result in 'Shift 2' and generator polynomial (A001H).
Generator polynomial (A001H) 1010 0000 0000 0001
Exclusive OR ( XOR) 1101 0000 0100 1111
Shift by 1 bit to the right. Shift 3 0110 1000 0010 0111 1
Since the flag is '1', calculate the exclusive OR (XOR) from the
result in 'Shift 3' and generator polynomial (A001H).
Generator polynomial (A001H) 1010 0000 0000 0001
Exclusive OR (XOR) 1100 1000 0010 1110
Shift by 1 bit to the right. Shift 4 0110 0100 0001 0011 0
Shift by 1 bit to the right. Shift 5 0011 0010 0000 1001 1
Since the flag is '1', calculate the exclusive OR (XOR) from the
result in 'Shift 5' and generator polynomial (A001H).
Generator polynomial (A001H) 1010 0000 0000 0001
Exclusive OR (XOR) 1001 0010 0000 1000
Shift by 1 bit to the right. Shift 6 0100 1001 0000 0100 0
Shift by 1 bit to the right. Shift 7 0010 0100 1000 0010 0
Shift by 1 bit to the right. Shift 8 0001 0010 0100 0001 0
8 The final value is a calculated CRC value. CRC value 12H 41H
Address field Function code Error check
Lower 8 bits of the CRC value Upper 8 bits of the CRC value
02H 07H 41H 12H
CRC error checking procedure 16-bit register (MSB) Flag
*1
Start END
:
(3AH)
CR + LF
(0DH) (0AH)
Address field
2 characters
Function code
2 characters
Data Error check
n x 2 characters
(n = 0 to 252)
2 characters
Error check calculation range
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