MSI 970A-G46 Series - Memory Timing Configuration

2-12
BIOS Setup
MS-7693
Chapter 2
BIOS Setup
MS-7693
Chapter 2
the DRAM tmngs for each channel and the followng related “Advanced DRAM
Con󰘰guraton” sub-menu manually.
Advanced DRAM Con󰘰guraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS
(column address strobe). The less clock cycles, the faster the DRAM performance.
tRP
Controls number of cycles for RAS (row address strobe) to be allowed to pre-charge.
If nsu󰘲cent tme s allowed for RAS to accumulate before DRAM refresh, the DRAM
may fal to retan data. Ths tem apples only when synchronous DRAM s nstalled
n the system.
tRAS
Determnes the tme RAS (row address strobe) takes to read from and wrte to
memory cell.
tRFC
Ths settng determnes the tme RFC takes to read from and wrte to a memory
cell.
tWR
Determnes mnmum tme nterval between end of wrte data burst and the start of a
pre-charge command. Allows sense ampl󰘰ers to restore data to cell.
tWTR
Determnes mnmum tme nterval between the end of wrte data burst and the start
of a column-read command; allows I/O gatng to overdrve sense ampl󰘰es before
read command starts.
tRRD
Spec󰘰es the actve-to-actve delay of d󰘯erent banks.
tRTP
Tme nterval between a read and a precharge command.
tFAW
Ths tem s used to set the tFAW (four actvate wndow delay) tmng.
tWCL
Ths tem s used to set the tWCL (Wrte CAS Latency) tmng.
tCKE
Ths tem s used to set the Pulse Wdth for DRAM module.
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