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BIOS Setup
Memory Timings
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto By SPD] enables DRAM timings
and the following related items to be determined by BIOS based on the configu-
rations on the SPD. Selecting [Manual] allows users to configure the DRAM
timings and the following related items manually.
TCL (CAS Latency)
When the Memory Timings sets to [Manual], the field is adjustable.This con-
trols the CAS latency, which determines the timing delay (in clock cycles) before
SDRAM starts a read command after receiving it.
TRCD
When the Memory Timings sets to [Manual], the field is adjustable. When
DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
TRP
When the Memory Timings sets to [Manual], the field is adjustable. This item
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
TRAS
When the Memory Timings sets to [Manual], the field is adjustable. This setting
determines the time RAS takes to read from and write to a memory cell.
CMD
This field controls the SDRAM command rate. Selecting [1T] makes SDRAM
signal controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes SDRAM
signal controller run at 2T rate.
TRRD
When the Memory Timings sets to [Manual], the field is adjustable. Specifies
the active-to-active delay of different banks.
TRC
When the Memory Timings sets to [Manual], the field is adjustable. The row
cycle time determines the minimum number of clock cycles a memory row takes
to complete a full cycle, from row activation up to the precharging of the active
row.
TWR
When the Memory Timings is set to [Manual], the field is adjustable. It speci-
fies the amount of delay (in clock cycles) that must elapse after the completion
of a valid write operation, before an active bank can be precharged. This delay
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