MSI P55-GD65 series - Page 50

En-40
MS-7583 Manboard ▍
CH1/ CH2 tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
CH1/ CH2 tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsu󰘲cent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refresh may be ncomplete and DRAM may fal to
retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
CH1/ CH2 tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
CH1/ CH2 tRFC
Ths settng determnes the tme RFC takes to read from and wrte to a memory
cell.
CH1/ CH2 tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense ampl󰘰ers to restore data to cells.
CH1/ CH2 tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a column-
read command. It allows I/O gatng to overdrve sense ampl󰘰ers before read
command starts.
CH1/ CH2 tRRD
Spec󰘰es the actve-to-actve delay of d󰘯erent banks.
CH1/ CH2 tRTP
Tme nterval between a read and a precharge command.
CH1/ CH2 tFAW
Ths tem s used to set the tFAW tmng.
Current CH1/ CH2 tdrRdTRd/ tddRdTRd/ tsrRdTWr/ tdrRdTWr/ tddRdTWr/
tsrWrTRd/ tddWrTWr/ tsrRDTRd/ tsrWrTWr
These tem show the advanced DRAM tmngs.
Channel 1/ Channel2 Advanced Memory Settng
Settng to [Auto] enables the advance memory tmng automatcally to be determned
by BIOS. Settng to [Manual] allows you to set the followng advanced memory
tmngs.
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