MSI Z68A-GD65 series

BIOS Setup
MS-7681
Chapter 3
3-9
BIOS Setup
MS-7681
Chapter 3
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsu󰘲cent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
tRFC
Ths settng determnes the tme RFC takes to read from and wrte to a memory
cell.
tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense ampl󰘰ers to restore data to cells.
tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a col
-
umn-read command. It allows I/O gatng to overdrve sense ampl󰘰ers before read
command starts.
tRRD
Spec󰘰es the actve-to-actve delay of d󰘯erent banks.
tRTP
Tme nterval between a read and a precharge command.
tFAW
Ths tem s used to set the tFAW (four actvate wndow delay) tmng.
tWCL
Ths tem s used to set the tWCL (Wrte CAS Latency) tmng.
tCKE
Ths tem s used to set the tCKE tmng.
Advanced Channel 1/ 2 Tmng Con󰘰guraton
Press <Enter> to enter the sub-menu. And you can set the advanced memory tmng
for each channel.
tRRDR/ tRRDD/ tWWDR/ tWWDD/ tRWDRDD/ tWRDRDD/ tRWSR
These tems s used to set the memory tmngs for memory channel 1/ 2.
GT OverClockng
Ths tem allows you to enable/ dsable the overclockng of ntegrated graphcs.
GT Rato
Ths settng controls the rato of ntegrated graphcs frequency to enable the ntegrated
graphcs to run at d󰘯erent frequency combnatons.
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