Home
Nations
Microcontrollers
N32G430 Series
Nations N32G430 Series User Manual
647 pages
Manual
Specs
Ask a question
To Next Page
To Next Page
Loading...
N32G430 series
32-bit
ARM
®
Cortex®
-M4 micr
ocontr
oller
User manual V1.0
2
Table of Contents
Table of Contents
2
List of Table
17
Abbreviations in the Text
28
Available Peripherals
28
List of Abbreviations for Registers
28
Bus Architecture
29
Figure 2-1 Bus Architecture
29
Memory and Bus Architecture
29
System Architecture
29
Bus Address Mapping
30
Figure 2-2 Bus Address Map
31
Table 2-1 List of Peripheral Register Addresses
32
Boot Management
34
FLASH Specification
35
Memory System
35
Table 2-2 List of Boot Mode
35
Table 2-3 Flash Bus Address List
36
Table 2-4 Option Byte List
40
Table 2-5 Read Protection Configuration List
42
Table 2-6 Flash Read-Write-Erase Permission Control Table
43
Icache
47
Sram
49
FLASH Register Description
50
Table 2-7 FLASH Register Overview
50
General Description
58
Power Control (PWR)
58
Power Supply
58
Figure 3-1 Power Supply Block Diagram
59
Power Supply Supervisor
59
Figure 3-2 Power on Reset/Power down Reset Waveform
60
Figure 3-3 PVD Threshold Diagram
60
Nrst
61
Power Modes
61
Table 3-1 Power Modes
61
Table 3-2 Modules Running Status
62
SLEEP Mode
63
STOP0 Mode
64
STOP2 Mode
65
STANDBY Mode
66
Power Control Register (PWR_CTRL)
67
PWR Register Overview
67
PWR Registers
67
Table 3-3 PWR Register Overview
67
Power Control Status Register (PWR_CTRLSTS)
69
Power Control Register 2(PWR_CTRL2)
71
General Description
73
Power Reset
73
Reset and Clock Control (RCC)
73
Reset Control Unit
73
System Reset
73
Figure 4-1 System Reset Generation
74
Backup Domain Reset
75
Clock Control Unit
75
Clock Tree Diagram
76
Figure 4-2 Clock Tree
76
HSE Clock
76
Figure 4-3 HSE Clock Source
77
HSI Clock
77
LSE Clock
78
LSI Clock
78
PLL Clock
78
Clock Security System (CLKSS)
79
LSE Clock Security System (LSECSS)
79
System Clock (SYSCLK) Selection
79
Clock Output(MCO)
80
RTC Clock
80
Watchdog Clock
80
RCC Register Overview
81
RCC Registers
81
Table 4-1 RCC Register Overview
81
Clock Control Register (RCC_CTRL)
82
Clock Configuration Register (RCC_CFG)
84
Clock Interrupt Register (RCC_CLKINT)
87
APB2 Peripheral Reset Register (RCC_APB2PRST)
89
APB1 Peripheral Reset Register (RCC_APB1PRST)
91
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
92
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
94
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
95
Backup Domain Control Register (RCC_BDCTRL)
97
Clock Control/Status Register (RCC_CTRLSTS)
98
AHB Peripheral Reset Register (RCC_AHBPRST)
100
Clock Configuration Register 2 (RCC_CFG2)
101
Retention Domain Control Register (RCC_RDCTRL)
102
AHB Peripheral Clock Enable Register 1 (RCC_AHB1CLKEN)
103
PLL and HSI Configuration Register (RCC_PLLHSIPRE)
103
GPIO and AFIO
105
Summary
105
Figure 5-1 5V Tolerant I/O Structure
106
Function Description
106
I/O Mode Configuration
106
Table 5-1 I/O Port Configuration Table
106
Table 5-2 I/O List of Functional Features of the Pin
107
Figure 5-2 Alternate Function Mode
108
Figure 5-3 Input Floating / Pull-Up / Pull-Down Configuration Mode
109
Figure 5-4 Output Mode
110
Figure 5-5 Analog Input Configuration with High Impedance
110
Atomic Bit Set and Reset
111
Status after Reset
111
Table 5-3 Special Pins after Reset
111
External Interrupt /Wakeup Line
112
Figure 5-6 EXTI Global Interrupts
112
Alternate Function
113
Table 5-4 Debug Interface Signal
114
Table 5-5 Debug Port Image
114
Table 5-6 ADC External Trigger Injected Conversion Alternate Function Remapping
115
Table 5-7 ADC External Trigger Regular Conversion Alternate Function Remapping
115
Table 5-8 TIM1 Alternate Function Remapping
115
Table 5-10 TIM3 Alternate Function Remapping
116
Table 5-11 TIM4 Alternate Function Remapping
116
Table 5-9 TIM2 Alternate Function Remapping
116
Table 5-12 TIM5 Alternate Function Remapping
117
Table 5-13 TIM8 Alternate Function Remapping
117
Table 5-14 LPTIM Alternate Function Remapping
118
Table 5-15 CAN Alternate Function Remapping
118
Table 5-16 USART1 Alternate Function Remapping
118
Table 5-17 USART2 Alternate Function Remapping
119
Table 5-18 UART3 Alternate Function Remapping
119
Table 5-19 UART4 Alternate Function Remapping
120
Table 5-20 I2C1 Alternate Function Remapping
120
Table 5-21 I2C2 Alternate Function Remapping
121
Table 5-22 SPI1/I2S1 Alternate Function Remapping
121
Table 5-23 SPI2/I2S2 Alternate Function Remapping
122
Table 5-24 COMP1 Alternate Function Remapping
122
Table 5-25 COMP2 Alternate Function Remapping
122
Table 5-26 COMP3 Alternate Function Remapping
123
Table 5-27 EVENTOUT Alternate Function Remapping
123
Table 5-28 BEEPER Alternate Function Remapping
123
Table 5-29 JTAG/SWD Alternate Function Remapping
123
Table 5-30 TIMESTAMP Alternate Function Remapping
123
I/O Configuration of Peripherals
124
Table 5-31 RTC_REFIN Alternate Function Remapping
124
Table 5-32 MCO Alternate Function Remapping
124
Table 5-33 ADC
124
Table 5-34 TIM1/TIM8
124
Table 5-35 TIM2/3/4/5
124
Table 5-36 LPTIM
124
Table 5-37 CAN
124
Table 5-38 USART
125
Table 5-39 UART
125
Table 5-40 I2C
125
Table 5-41 SPI-I2S
125
Table 5-42 JTAG/SWD
125
GPIO Locking Mechanism
126
Table 5-43 RTC
126
Table 5-44 COMP
126
Table 5-45 EVENT_OUT
126
Table 5-46 Other
126
GPIO Registers
127
GPIOA Register Overview
127
Table 5-47 GPIOA Register Overview
127
GPIOB Register Overview
129
Table 5-48 GPIOB Register Overview
129
GPIOC Register Overview
130
Table 5-49 GPIOC Register Overview
130
GPIOD Register Overview
132
Table 5-50 GPIOD Register Overview
132
GPIO Port Mode Description Register (Gpiox_Pmode)
133
GPIO Port Type Definition (Gpiox_Potype)
134
GPIO Port Pull-Up/Pull-Down Description Register (Gpiox_Pupd)
135
GPIO Slew Rate Configuration Register (Gpiox_Sr)
135
GPIO Port Input Data Register (Gpiox_Pid)
136
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
137
GPIO Port Output Data Register (Gpiox_Pod)
137
GPIO Port Bit Clear Register (Gpiox_Pbc)
138
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)
139
GPIO Alternate Function High Register (Gpiox_Afh)
140
GPIO Alternate Function Low Register (Gpiox_Afl)
140
GPIO Driver Strength Configuration Register (Gpiox_ DS)
141
AFIO Register Overview
142
AFIO Registers
142
Table 5-51 AFIO Register Overview
142
Alternate Function Mapping Configuration Control Register (AFIO_RMP_CFG)
144
External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)
144
External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)
151
External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)
158
External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)
165
Tolerance Configuration Register (AFIO_TOL5V
172
Analog Filter Configuration Register 1 (AFIO_EFT_CFG1)
174
Analog Filter Configuration Register 2 (AFIO_EFT_CFG2)
174
Digital Glitch Filter Stage (Glitch Width) Configuration Register (AFIO_FILT_CFG)
175
Digital Glitch Filter Configuration Register 1 (AFIO_DIGEFT_CFG1)
176
Digital Glitch Filter Configuration Register 2 (AFIO_DIGEFT_CFG2)
176
Interrupt and Exception Vectors
178
Interrupts and Events
178
Nested Vectored Interrupt Controller
178
Systick Calibration Value Register
178
Table 6-1 Vector Table
178
External Interrupt/Event Controller (EXTI)
181
EXTI Main Features
181
Introduction to EXTI
181
Figure 6-1 EXTI Functional Diagram
182
Functional Description
182
EXTI Line Mapping
184
Figure 6-2 External Interrupt GPIO Mapping
184
EXTI Register Overview
185
EXTI Registers
185
Interrupt Mask Register(EXTI_IMASK)
185
Table 6-2 EXTI Register Overview
185
Event Mask Register(EXTI_EMASK)
186
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
186
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
187
Software Interrupt Event Register(EXTI_SWIE)
187
Interrupt Request Pending Register(EXTI_PEND)
188
RTC Timestamp Selection Register(EXTI_TS_SEL)
188
DMA Controller
190
Introduction
190
Main Features
190
Block Diagram
191
DMA Operation
191
Figure 7-1 DMA Block Diagram
191
Function Description
191
Channel Priority and Arbitration
192
DMA Channels and Number of Transfers
192
Programmable Data Bit Width, Alignment and Endians
192
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
192
Channel Configuration Procedure
194
Peripheral/Memory Address Incrementation
194
Circular Mode
195
Flow Control
195
Table 7-2 Flow Control Table
195
DMA Request Mapping
196
Error Management
196
Interrupt
196
Table 7-3 DMA Interrupt Request
196
Table 7-4 DMA Request Mapping
196
DMA Register Overview
199
DMA Registers
199
Table 7-5 DMA Register Overview
199
DMA Interrupt Status Register (DMA_INTSTS)
200
DMA Interrupt Flag Clear Register (DMA_INTCLR)
201
DMA Channel X Configuration Register (Dma_Chcfgx)
202
DMA Channel X Transfer Number Register (Dma_Txnumx)
203
DMA Channel X Memory Address Register (Dma_Maddrx)
204
DMA Channel X Peripheral Address Register (Dma_Paddrx)
204
DMA Channel X Channel Request Select Register (Dma_Chselx)
205
CRC Calculation Unit
207
CRC Introduction
207
CRC Main Features
207
CRC16 Module
207
CRC32 Module
207
CRC Function Description
208
Crc16
208
Crc32
208
Figure 8-1 CRC Calculation Unit Block Diagram
208
CRC Register Overview
209
CRC Registers
209
CRC32 Data Register (CRC_CRC32DAT)
209
CRC32 Independent Data Register (CRC_CRC32IDAT)
209
Table 8-1 CRC Register Overview
209
CRC16 Control Register (CRC_CRC16CTRL)
210
CRC32 Control Register (CRC_CRC32CTRL)
210
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
211
CRC16 Input Data Register (CRC_CRC16DAT)
211
LRC Result Register (CRC_LRC)
212
Advanced-Control Timers (TIM1 and TIM8)
213
Main Features of TIM1 and TIM8
213
TIM1 and TIM8 Introduction
213
Figure 9-1 Block Diagram of TIM1
214
Figure 9-2 Block Diagram of TIM8
215
TIM1 and TIM8 Function Description
215
Time-Base Unit
215
Counter Mode
216
Figure 9-3 Counter Timing Diagram with Prescaler Division Change from 1 to 4
216
Figure 9-4 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
217
Figure 9-5 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
218
Figure 9-6 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
219
Figure 9-7 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
220
Figure 9-8 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
221
Figure 9-9 the Output Waveform Corresponding to the Asymmetric Mode
223
Figure 9-10 Ccdatx(X=4,7,8,9), Trigger ADC When dir = 0
224
Figure 9-11 Ccdatx(X=4,7,8,9), Trigger ADC When dir = 1
225
Figure 9-12 Ccdatx(X=4,7,8,9), Trigger ADC When dir = 0 or dir = 1
226
Repetition Counter
226
Figure 9-13 Repeat Count Sequence Diagram in Down-Counting Mode
227
Figure 9-14 Repeat Count Sequence Diagram in Up-Counting Mode
227
Clock Selection
228
Figure 9-15 Repeat Count Sequence Diagram in Center-Aligned Mode
228
Figure 9-16 Control Circuit in Normal Mode, Internal Clock Divided by 1
229
Figure 9-17 TI2 External Clock Connection Example
229
Figure 9-18 Control Circuit in External Clock Mode 1
230
Figure 9-19 External Trigger Input Block Diagram
231
Figure 9-20 Control Circuit in External Clock Mode 2
231
Capture/Compare Channels
232
Figure 9-21 Capture/Compare Channel (Example: Channel 1 Input Stage)
232
Figure 9-22 Capture/Compare Channel 1 Main Circuit
233
Figure 9-23 Output Part of Channelx (X= 1,2,3,4 for TIM1; X= 1,2,3 for TIM8. Take Channel 1 as Example)
234
Figure 9-24 Output Part of Channelx (for TIM8, X= 4)
234
Input Capture Mode
234
PWM Input Mode
235
Figure 9-25 PWM Input Mode Timing
236
Forced Output Mode
236
Output Compare Mode
237
Figure 9-26 Output Compare Mode, Toggle on OC1
238
PWM Mode
238
Figure 9-27 Center-Aligned PWM Waveform (AR=8)
239
Figure 9-28 Edge-Aligned PWM Waveform (APR=8)
240
Figure 9-29 Example of One-Pulse Mode
241
One-Pulse Mode
241
Clearing the Ocxref Signal on an External Event
242
Complementary Outputs with Dead-Time Insertion
243
Figure 9-30 Clearing the Ocxref of Timx
243
Figure 9-31 Complementary Output with Dead-Time Insertion
244
Break Function
245
Figure 9-32 Output Behavior in Response to a Break
246
Debug Mode
247
Figure 9-33 Slide Filter
247
Timx and External Trigger Synchronization
247
Figure 9-34 Control Circuit in Reset Mode
248
Figure 9-35 Control Circuit in Trigger Mode
249
Figure 9-36 Control Circuit in Gated Mode
249
6-Step PWM Generation
251
Figure 9-37 Control Circuit in Trigger Mode + External Clock Mode2
251
Timer Synchronization
251
Encoder Interface Mode
252
Figure 9-38 6-Step PWM Generation, COM Example (OSSR=1)
252
Figure 9-39 Example of Counter Operation in Encoder Interface Mode
253
Table 9-1 Counting Direction Versus Encoder Signals
253
Figure 9-40 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
254
Interfacing with Hall Sensor
255
Figure 9-41 Example of Hall Sensor Interface
256
Register Overview
257
Table 9-2 Register Overview
257
Timx Register Description(X=1, 8)
257
Control Register 1 (Timx_Ctrl1)
260
Control Register 2 (Timx_Ctrl2)
262
Slave Mode Control Register (Timx_Smctrl)
265
Dma/Interrupt Enable Registers (Timx_Dinten)
267
Table 9-3 Timx Internal Trigger Connection
267
Status Registers (Timx_Sts)
269
Event Generation Registers (Timx_Evtgen)
271
Capture/Compare Mode Register 1 (Timx_Ccmod1)
272
Capture/Compare Mode Register 2 (Timx_Ccmod2)
275
Capture/Compare Enable Registers (Timx_Ccen)
277
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
279
Counters (Timx_Cnt)
280
Prescaler (Timx_Psc)
280
Auto-Reload Register (Timx_Ar)
281
Capture/Compare Register 1 (Timx_Ccdat1)
281
Repeat Count Registers (Timx_Repcnt)
281
Capture/Compare Register 2 (Timx_Ccdat2)
282
Capture/Compare Register 3 (Timx_Ccdat3)
283
Capture/Compare Register 4 (Timx_Ccdat4)
284
Break and Dead-Time Registers (Timx_Bkdt)
285
DMA Control Register (Timx_Dctrl)
286
DMA Transfer Buffer Register (Timx_Daddr)
287
Figure 10-1 Block Diagram of Timx(X = 2, 3, 4 and 5
294
Time-Base Unit
294
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
295
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
297
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
298
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
299
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
300
Clock Selection
301
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
301
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
302
Figure 10-9 TI2 External Clock Connection Example
303
Figure 10-10 Control Circuit in External Clock Mode 1
304
Figure 10-11 External Trigger Input Block Diagram
304
Figure 10-12 Control Circuit in External Clock Mode 2
305
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
306
Figure 10-14 Capture/Compare Channel 1 Main Circuit
307
Figure 10-15 Output Part of Channelx (X=1/2/3/4. Take Channel 4 as Example
308
Figure 10-16 Slide Filter
309
Figure 10-17 PWM Input Mode Timing
310
Figure 10-18 Output Compare Mode, Toggle on OC1
312
Figure 10-19 Center-Aligned PWM Waveform (AR=8)
313
Figure 10-20 Edge-Aligned PWM Waveform (APR=8)
314
Figure 10-21 Example of One-Pulse Mode
315
Debug Mode
317
Figure 10-22 Control Circuit in Reset Mode
317
Figure 10-23 Control Circuit in Reset Mode
318
Figure 10-24 Control Circuit in Trigger Mode
319
Figure 10-25 Control Circuit in Gated Mode
320
Figure 10-26 Control Circuit in Trigger Mode + External Clock Mode2
321
Figure 10-27 Block Diagram of Timer Interconnection
322
Figure 10-28 TIM2 Gated by OC1REF of TIM1
323
Figure 10-29 TIM2 Gated by Enable Signal of TIM1
324
Figure 10-30 Trigger TIM2 with an Update of TIM1
324
Figure 10-31 Triggers Timers 1 and 2 Using the TI1 Input of TIM1
325
Table 10-1 Counting Direction Versus Encoder Signals
326
Figure 10-32 Example of Counter Operation in Encoder Interface Mode
327
Figure 10-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
327
Register Overview
329
Table 10-2 Register Overview
329
Control Register 1 (Timx_Ctrl1)
330
Dma/Interrupt Enable Registers (Timx_Dinten)
336
Table 10-3 Timx Internal Trigger Connection
336
Status Registers (Timx_Sts)
337
Event Generation Registers (Timx_Evtgen)
339
Auto-Reload Register (Timx_Ar)
346
Counters (Timx_Cnt)
346
Prescaler (Timx_Psc)
346
Table 10-4 Output Control Bits of Standard Ocx Channel
346
Figure 11-1 Block Diagram of Timx(X = 6
355
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
356
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
357
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
358
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
359
Table 11-1 Register Overview
360
Figure 12-1 LPTIM Diagram
365
Table 12-1 Pre-Scalar Division Ratios
366
Figure 12-2 Glitch Filter Timing Diagram
367
Table 12-2 9 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[3:0] Bits
367
Figure 12-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
369
Figure 12-4 PTIM Output Waveform, Single Counting Mode Configuration
370
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration and Set-Once Mode Activated
370
Figure 12-6 Waveform Generation
372
Table 12-3 Encoder Counting Scenarios
374
Figure 12-7 Encoder Mode Counting Sequence
375
Figure 12-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
376
Figure 12-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
376
Table 12-4 Interruption Events
377
Table 12-5 LPTIM Register Overview
378
Figure 13-1 Functional Block Diagram of the Independent Watchdog Module
388
Table 13-1 IWDG Counting Maximum and Minimum Reset Time
390
Table 13-2 IWDG Register Overview
390
Figure 14-1 Watchdog Block Diagram
394
Figure 14-2 Refresh Window and Interrupt Timing of WWDG
395
Table 14-1 Maximum and Minimum Counting Time of WWDG
396
Table 14-2 WWDG Register Overview
397
Figure 15-1 Block Diagram of a Single ADC
400
Table 15-1 ADC Pins
400
Figure 15-2 ADC Clock
402
Figure 15-3 ADC Channels and Pin Connections
403
Figure 15-4 Timing Diagram
405
Table 15-2 Analog Watchdog Channel Selection
405
Figure 15-5 Injection Conversion Delay
407
Figure 15-6 Calibration Sequence Diagram
408
Table 15-3 Right-Align Data
409
Table 15-4 Left-Aligne Data
409
Table 15-5 ADC Is Used for External Triggering of Regular Channels
410
Table 15-6 ADC Is Used for External Triggering of Injection Channels
411
Figure 15-7 Temperature Sensor and VREFINT Diagram of the Channel
412
Table 15-7 ADC Interrupt
413
Table 15-8 ADC Register Overview
414
Figure 16-1 Comparator Controller Functional Diagram
430
Table 16-1 COMP Register Overview
434
Figure 17-1 Functional Block Diagram of I 2 C
451
Figure 17-2 I2C Bus Protocol
451
Figure 17-3 Transfer Sequence Diagram Slave Transmitter
454
Figure 17-4 Transfer Sequence Diagram of Slave Receiver
455
Figure 17-5 Master Transmitter Transmission Sequence Diagram
457
Figure 17-6 Master Receiver Transmission Sequence Diagram
459
Table 17-1 Comparison between Smbus and I2C
463
Table 17-2 I 2 C Interrupt Request
465
Table 17-3 I2C Register Overview
466
Figure 18-1 USART Block Diagram
480
Figure 18-2 Word Length = 8 Setting
482
Figure 18-3 Word Length = 9 Setting
482
Figure 18-4 Configuration Stop Bit
483
Table 18-1 Stop Bit Configuration
483
Figure 18-5 TXC/TXDE Changes During Transmission
485
Figure 18-6 Start Bit Detection
486
Table 18-2 Data Sampling for Noise Detection
488
Table 18-3 Error Calculation When Setting Baud Rate
490
Table 18-4 When Div_Fraction = 0. Tolerance of USART Receiver
491
Table 18-5 When Div_Fraction != 0, Tolerance of USART Receiver
491
Table 18-6 Frame Format
491
Figure 18-7 Transmission Using DMA
493
Figure 18-8 Reception Using DMA
494
Figure 18-9 Hardware Flow Control between Two USART
494
Figure 18-10 RTS Flow Control
495
Figure 18-11 CTS Flow Controls
496
Figure 18-12 Mute Mode Using Idle Line Detection
497
Figure 18-13 Mute Mode Detected Using Address Mark
498
Figure 18-14 USART Synchronous Transmission Example
499
Figure 18-15 USART Data Clock Timing Example (WL=0)
500
Figure 18-16 USART Data Clock Timing Example (WL=1)
501
Figure 18-17 RX Data Sampling / Holding Time
501
Figure 18-18 Irdasirendec-Block Diagram
503
Figure 18-19 Irda Data Modulation (3/16)-Normal Mode
503
Figure 18-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
505
Figure 18-21 Break Detection and Framing Error Detection in LIN Mode
506
Figure 18-22 ISO7816-3 Asynchronous Protocol
507
Figure 18-23 Use 1.5 Stop Bits to Detect Parity Errors
508
Table 18-7 USART Interrupt Request
508
Table 18-9 USART Register Overview
509
Figure 19-1 SPI Block Diagram
522
Figure 19-2 Selective Management of Hardware/Software
523
Figure 19-3 Master and Slave Applications
524
Figure 19-4 Data Clock Timing Diagram
525
Figure 19-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode
526
(BIDIRMODE=0 and RONLY=1)
527
Figure 19-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode
527
Figure 19-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode
527
Figure 19-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in
529
Figure 19-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional
529
Full Duplex Mode
529
Transmit-Only Mode
529
Discontinuously
531
Figure 19-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
531
Figure 19-11 Transmission Using DMA
534
Figure 19-12 Reception Using DMA
534
Table 19-1 SPI Interrupt Request
536
Figure 19-13 I S Block Diagram
537
Figure 19-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
539
Figure 19-15 I S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
539
Figure 19-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
541
Figure 19-18 MSB Aligns 24-Bit Data, CLKPOL = 0
541
Figure 19-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
542
Figure 19-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
542
Figure 19-21 LSB Aligns 24-Bit Data, CLKPOL = 0
543
Figure 19-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
543
Figure 19-23 PCM Standard Waveform (16 Bits)
544
Figure 19-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
544
Figure 19-25 I S Clock Generator Structure
545
Figure 19-26 Audio Sampling Frequency Definition
545
Table 19-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
546
Table 19-3 I 2 S Interrupt Request
549
Table 19-4 SPI Register Overview
550
Table 20-1 RTC Feature Support
560
Figure 20-1 RTC Block Diagram
561
Table 20-2 RTC Register Overview
570
Table 21-1 Max and Min Frequency Supported by Beeper and Corresponding Configure
590
Table 21-2 Beeper Register Overview
591
Figure 22-1 Topology of CAN Network
594
Figure 22-2 CAN Working Mode
596
Figure 22-3 Single CAN Block Diagram
597
Figure 22-4 Loopback Mode
598
Figure 22-5 Silent Mode
599
Figure 22-6 Loopback Silent Mode
599
Figure 22-7 Send Mailbox Status
602
Figure 22-8 Receive FIFO Status
603
Figure 22-9 Filter Bit Width Setting-Register Organization
605
Table 22-1 Examples of Filter Numbers
606
Figure 22-10 Examples of Filter Mechanisms
607
Table 22-2 Send Mailbox Register List
608
Table 22-3 Receive Mailbox Register List
608
Figure 22-11 Bit Sequence
609
Figure 22-12 Various CAN Frames
610
Figure 22-13 Event Flag and Interrupt Generation
611
Figure 22-14 CAN Error State Diagram
612
Table 22-4 CAN Register Overview
615
Figure 23-1 N32G430 Level and Cortex®-M4 Level Debugging Block Diagram
639
Table 23-1 Debug Port Pin
641
Table 23-2 DBG Register Overview
642
Need help?
Do you have a question about the Nations N32G430 Series and is the answer not in the manual?
Ask a question
Nations N32G430 Series Specifications
General
Core Architecture
ARM Cortex-M0
Temperature Range
-40°C to +85°C
ADC
12-bit
ADC Channels
up to 16
Communication Interfaces
I2C, SPI, UART
Package
LQFP48
Related product manuals
Nations N32G45 Series
838 pages