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Provides an overview of the NCR Century 200 processor's function and features.
Details the processor's architecture, addressing flexibility, and hardware usage.
Explains the interrupt handling mechanisms within the NCR Century 200 processor.
Details memory size options up to 512K and memory upgrades.
Explains how trunk bandwidth is increased by converting trunks.
Describes the octaplex system and its four-way simultaneity.
Covers concurrent execution of programs and memory protection.
Explains the floating point option for computations involving fractions.
Describes commands for Boolean logic operations and data comparison.
Details the multiplex command for decimal multiplication.
Explains the interval timer for multiprogramming and real-time clock functions.
Describes the trace option for monitoring program execution.
Enables execution of 315 programs using specific registers.
Allows simulation of IBM 1401, 1440, and 1460 systems.
Details the thermal printer's functionality for I/O operations.
Explains the system's audible and visual alarm features for operators.
Lists and briefly describes various optional peripherals available for the system.
Describes the NCR Century 200 system's basic configuration and expansion capabilities.
Details the standard configuration of the NCR Century 200 system.
Describes the physical characteristics of the NCR Century 200 memory.
Explains how data is represented in the NCR Century Code and BCD.
Provides examples illustrating data representation in BCD and NCR Century code.
Details how memory locations are addressed and the concept of effective addresses.
Explains the function and usage of index registers for addressing flexibility.
Provides a detailed table of index registers and reserved memory areas.
Introduces the Arithmetic Logic Unit (ALU) and its hardware-oriented design.
Details the command structure, including command code and operand formats.
Explains the RA character's role in specifying addressing modes.
Details addressing Mode 0, including no indexing and A2A1 characters.
Explains addressing Mode 1 with intermediate effective addresses.
Details addressing Mode 2, including indirect addressing.
Explains addressing Mode 3 with incremental indexing.
Describes the A2A1 characters for partial addresses and effective addresses.
Explains the T portion of the command specifying field length.
Details the RB character's function related to the B operand.
Explains the B2B1 characters related to the B operand.
Discusses the processor's operation without waiting for clock signals.
Describes registers that contain current operational data.
Details specialized registers used for specific functions like BAR/LAR.
Explains the standard hardware flags indicating operation conditions.
Lists processor indicators and their functions for command status.
Describes the ALU's functional operation in control, addressing, and data transfer.
Explains the control section's role in regulating data transfer and command execution.
Details the addressing function and data paths to the address register.
Describes the adder's function for arithmetic operations.
Explains the MA, MB, TT, T, ID registers and their data flow.
Illustrates how processor registers are expanded with memory options.
Details the three phases of command processing: setup, execution, and testing.
Defines Between Commands Testing (BCT) as a series of tests for processor ability.
Explains how BCT impacts program flow, halting, or continuation.
Describes how the Error Indicator (EI) causes a processor error halt.
Explains the detection and function of the Memory Error (ME) indicator.
Details how PE and CCI indicators signify errors or trap conditions.
Explains how the Repeat Indicator (RI) functions during REPEAT commands.
Describes the Trace Permit (TP) option for monitoring command execution.
Explains interrupt permit and indicator functions for I/O operations.
Describes the effect of the HALT button on command execution.
Introduces I/O operations initiated by the ALU and peripheral selection.
Explains the common trunk concept and I/O control functions.
Details trunk assignments for integrated and freestanding peripherals.
Describes the Quadraplex and Octaplex system configurations.
Explains data transfer, bandwidth, and system bandwidth.
Differentiates between integrated and freestanding peripherals.
Outlines the I/O operation phases: selection, data transfer, and termination.
Details the Trace option and its commands for monitoring execution.
Explains the process of executing trace commands and their effects.
Describes using the monitor switch with the trace option.
Explains the monitor register's use for storing memory addresses.
Enhances the system with eight simultaneous I/O operations.
Increases I/O bandwidth by utilizing high-speed trunks.
Allows multiple programs to share memory and processor resources.
Differentiates between user and supervisor modes based on the S flag.
Explains the function of BAR and LAR for memory protection and addressing.
Details BAR/LAR usage in the user state for command processing.
Explains BAR/LAR usage in the supervisor state for command processing.
Describes BAR's role in handling branches and status flags.
Lists commands that require supervisor state execution.
Covers console features like HALT button and manual operation.
Details the interval timer's function and accuracy.
Lists memory sizes available with the extended memory option.
Explains addressing with index registers and displacement values.
Enables execution of 315 programs using specific registers.
Allows simulation of IBM 1401, 1440, and 1460 systems.
Provides commands for floating point arithmetic operations.
Describes the operator's console for interaction and system monitoring.
Introduces the integrated I/O writer for enhanced peripheral communication.
Details the physical characteristics of the standard and thermal I/O writers.
Describes the pin-feed platen printer with keyboard input.
Explains the thermal printer using heat-sensitive paper.
Covers the functionality of a second I/O writer located remotely.
Refers to other publications for functional descriptions of I/O writers.
Lists power requirements, KVA, BTU/HR, and circuit breaker details.
Outlines operating limits for temperature, humidity, and altitude.
Introduces hardware commands and command timing calculations.
Defines the publication's intent as a supplement for hardware commands.
Provides formulas for calculating total command time (setup + execution).
Lists basic hardware commands with their codes and starting page numbers.
Lists optional hardware commands, their codes, and starting page numbers.
Provides an overview of the NCR Century 200 processor's function and features.
Details the processor's architecture, addressing flexibility, and hardware usage.
Explains the interrupt handling mechanisms within the NCR Century 200 processor.
Details memory size options up to 512K and memory upgrades.
Explains how trunk bandwidth is increased by converting trunks.
Describes the octaplex system and its four-way simultaneity.
Covers concurrent execution of programs and memory protection.
Explains the floating point option for computations involving fractions.
Describes commands for Boolean logic operations and data comparison.
Details the multiplex command for decimal multiplication.
Explains the interval timer for multiprogramming and real-time clock functions.
Describes the trace option for monitoring program execution.
Enables execution of 315 programs using specific registers.
Allows simulation of IBM 1401, 1440, and 1460 systems.
Details the thermal printer's functionality for I/O operations.
Explains the system's audible and visual alarm features for operators.
Lists and briefly describes various optional peripherals available for the system.
Describes the NCR Century 200 system's basic configuration and expansion capabilities.
Details the standard configuration of the NCR Century 200 system.
Describes the physical characteristics of the NCR Century 200 memory.
Explains how data is represented in the NCR Century Code and BCD.
Provides examples illustrating data representation in BCD and NCR Century code.
Details how memory locations are addressed and the concept of effective addresses.
Explains the function and usage of index registers for addressing flexibility.
Provides a detailed table of index registers and reserved memory areas.
Introduces the Arithmetic Logic Unit (ALU) and its hardware-oriented design.
Details the command structure, including command code and operand formats.
Explains the RA character's role in specifying addressing modes.
Details addressing Mode 0, including no indexing and A2A1 characters.
Explains addressing Mode 1 with intermediate effective addresses.
Details addressing Mode 2, including indirect addressing.
Explains addressing Mode 3 with incremental indexing.
Describes the A2A1 characters for partial addresses and effective addresses.
Explains the T portion of the command specifying field length.
Details the RB character's function related to the B operand.
Explains the B2B1 characters related to the B operand.
Discusses the processor's operation without waiting for clock signals.
Describes registers that contain current operational data.
Details specialized registers used for specific functions like BAR/LAR.
Explains the standard hardware flags indicating operation conditions.
Lists processor indicators and their functions for command status.
Describes the ALU's functional operation in control, addressing, and data transfer.
Explains the control section's role in regulating data transfer and command execution.
Details the addressing function and data paths to the address register.
Describes the adder's function for arithmetic operations.
Explains the MA, MB, TT, T, ID registers and their data flow.
Illustrates how processor registers are expanded with memory options.
Details the three phases of command processing: setup, execution, and testing.
Defines Between Commands Testing (BCT) as a series of tests for processor ability.
Explains how BCT impacts program flow, halting, or continuation.
Describes how the Error Indicator (EI) causes a processor error halt.
Explains the detection and function of the Memory Error (ME) indicator.
Details how PE and CCI indicators signify errors or trap conditions.
Explains how the Repeat Indicator (RI) functions during REPEAT commands.
Describes the Trace Permit (TP) option for monitoring command execution.
Explains interrupt permit and indicator functions for I/O operations.
Describes the effect of the HALT button on command execution.
Introduces I/O operations initiated by the ALU and peripheral selection.
Explains the common trunk concept and I/O control functions.
Details trunk assignments for integrated and freestanding peripherals.
Describes the Quadraplex and Octaplex system configurations.
Explains data transfer, bandwidth, and system bandwidth.
Differentiates between integrated and freestanding peripherals.
Outlines the I/O operation phases: selection, data transfer, and termination.
Details the Trace option and its commands for monitoring execution.
Explains the process of executing trace commands and their effects.
Describes using the monitor switch with the trace option.
Explains the monitor register's use for storing memory addresses.
Enhances the system with eight simultaneous I/O operations.
Increases I/O bandwidth by utilizing high-speed trunks.
Allows multiple programs to share memory and processor resources.
Differentiates between user and supervisor modes based on the S flag.
Explains the function of BAR and LAR for memory protection and addressing.
Details BAR/LAR usage in the user state for command processing.
Explains BAR/LAR usage in the supervisor state for command processing.
Describes BAR's role in handling branches and status flags.
Lists commands that require supervisor state execution.
Covers console features like HALT button and manual operation.
Details the interval timer's function and accuracy.
Lists memory sizes available with the extended memory option.
Explains addressing with index registers and displacement values.
Enables execution of 315 programs using specific registers.
Allows simulation of IBM 1401, 1440, and 1460 systems.
Provides commands for floating point arithmetic operations.
Describes the operator's console for interaction and system monitoring.
Introduces the integrated I/O writer for enhanced peripheral communication.
Details the physical characteristics of the standard and thermal I/O writers.
Describes the pin-feed platen printer with keyboard input.
Explains the thermal printer using heat-sensitive paper.
Covers the functionality of a second I/O writer located remotely.
Refers to other publications for functional descriptions of I/O writers.
Lists power requirements, KVA, BTU/HR, and circuit breaker details.
Outlines operating limits for temperature, humidity, and altitude.
Introduces hardware commands and command timing calculations.
Defines the publication's intent as a supplement for hardware commands.
Provides formulas for calculating total command time (setup + execution).
Lists basic hardware commands with their codes and starting page numbers.
Lists optional hardware commands, their codes, and starting page numbers.
General| Brand | NCR |
|---|---|
| Model | Century 200 |
| Category | Computer Hardware |
| Language | English |
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