NXP Semiconductors UM11490 - Page 60

NXP Semiconductors
UM11490
Feature Configuration Guide for NXP-based Wireless Modules on i.MX 8M Quad EVK
Step 15 - Write PCM sync settings
root@imx8mqevk:~# hcitool -i hci0 cmd 0x3F 0x0028 0x03 0x00 0x03
Command output example:
< HCI Command: ogf 0x3f, ocf 0x0028, plen 3
03 00 03
> HCI Event: 0x0e plen 4
01 28 FC 00
root@imx8mqevk:~#
where:
Parameter Length Definition
OGF 1 0x3F
OCF 2 0x0028
PCM Sync Settings
1
1 Default = 0x03
ISR (IramSyncRate) only valid if IF = Host:
PCM Sync Settings 1 Bit[0]:
• 0 = bursts controlled by Tx or Rx of voice packets
• 1 = fixed rate of 8 ksample/s
ISS (IramSyncSource) only valid if IF = Host and ISR = Fixed
Rate:
PCM Sync Settings 1 Bit[1]:
• 0 = 0 = ISR not aligned to frame tick
• 1 = ISR aligned to frame tick (this field should be set to 1)
PCM Sync Settings
2
2 Default = 0x0000
pcmIfMode in PCM Descriptor
PCM Sync Settings 2 Bits[1:0]:
• 00 = PCM short sync
• 01 = PCM long sync
• 10 = I2S audio mode
pcmLRCPol in PCM Descriptor
PCM Sync Settings 2 Bit[4]:
• 0 = LRC is same polarity as PCM sync
• 1 = LRC is inverted
pcmMClkEn in PCM Descriptor
PCM Sync Settings 2 Bit[8]:
• 0 = disable generation of PCM main clock
• 1 = enable
pcm2048MClkSel in PCM Descriptor
PCM Sync Settings 2 Bit[9]:
• 0 = default
• 1 = select 2.048 MHz clock for PCM clock
16k Sync in PCM
PCM Sync Settings 2 Bit[10]:
• 0 = 8k Sync
• 1 = 16k Sync
UM11490 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 2 — 29 January 2021
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