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Omron SYSMAC C20K User Manual

Omron SYSMAC C20K
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31
When two or more conditions lie on separate instruction lines running in par-
allel and then joining together, the first condition corresponds to a LOAD or
LOAD NOT instruction; the rest of the conditions correspond to OR or OR
NOT instructions. The following example shows three conditions which corre-
spond in order from the top to a LOAD NOT, an OR NOT, and an OR instruc-
tion.
Instruction
0100
HR 000
0000
Address Instruction Operands
0000 LD 0000
0001 OR NOT 0100
0002 OR HR 000
0003 Instruction
The instruction at the right would have an ON execution condition when any
one of the three conditions was ON, i.e., when IR 0000 was OFF, when IR
0100 was OFF, or when HR 000 was ON.
OR and OR NOT instructions can also be considered individually, each tak-
ing the logical OR between its execution condition and the status of the OR
instruction’s operand bit. If either one of these were ON, an ON execution
condition would be produced for the next instruction.
When AND and OR instructions are combined in more complicated dia-
grams, they can sometimes be considered individually, with each instruction
performing a logic operation on the execution condition and the status of the
operand bit. The following is one example.
Instruction
0002 00030000 0001
0200
Address Instruction Operands
0000 LD 0000
0001 AND 0001
0002 OR 0200
0003 AND 0002
0004 AND NOT 0003
0005 Instruction
Here, an AND is taken between the status of 0000 and that of 0001 to deter-
mine the execution condition for an OR with the status of 0200. The result of
this operation determines the execution condition for an AND with the status
of 0002, which in turn determines the execution condition for an AND with the
inverse of the status of 0003. In more complicated diagrams, however, it is
necessary to consider logic blocks before an execution condition can be de-
termined for the final instruction, and that’s where AND LOAD and OR LOAD
instructions are used.
OR and OR NOT
Combining AND and OR
Instructions
The Ladder Diagram Section 4-3

Table of Contents

Other manuals for Omron SYSMAC C20K

Questions and Answers:

Omron SYSMAC C20K Specifications

General IconGeneral
ModelSYSMAC C20K
TypeProgrammable Logic Controller (PLC)
Program Capacity2000 steps
Operating Temperature0°C to 55°C
Humidity10% to 90% (non-condensing)
Instruction SetBasic instructions
Programming LanguageLadder logic
Power Supply100-240V AC

Summary

PRECAUTIONS

1 Intended Audience

Specifies the target audience and required knowledge for manual readers.

2 General Precautions

Outlines general rules for operating OMRON products safely and correctly.

3 Safety Precautions

Details critical safety warnings, including electric shock hazards.

4 Operating Environment Precautions

Lists environmental conditions to avoid for PC system operation.

5 Application Precautions

Provides essential safety guidelines for system installation and application usage.

SECTION 1 Background

1-1 Introduction

Introduces Programmable Controllers (PCs) and their basic operation.

1-2 Relay Circuits: The Roots of PC Logic

Explains the historical connection between relay logic and PC programming.

1-3 PC Terminology

Defines key terms like PC, input/output devices, and control systems.

1-4 OMRON Product Terminology

Clarifies OMRON-specific product terminology such as 'Unit'.

1-5 Overview of PC Operation

Outlines the basic steps for programming and operating a K-type PC.

1-6 Peripheral Devices

Describes devices used for PC programming and interfacing.

1-7 Available Manuals

Lists related manuals required for PC programming and operation.

SECTION 2 Hardware Considerations

2-1 Introduction

Provides information on hardware aspects relevant to programming.

2-2 Indicators

Explains the functions of CPU indicators for PC status monitoring.

2-3 PC Configuration

Describes the basic components of a K-type PC system.

SECTION 3 Memory Areas

3-1 Introduction

Explains the purpose of various memory areas for PC data management.

3-2 Data Area Structure

Details the organization and addressing of PC memory areas.

3-3 Internal Relay (IR) Area

Describes the IR area for I/O points, work bits, and control.

3-4 Special Relay (SR) Area

Covers SR area flags, clock pulses, and error indicators.

3-5 Data Memory (DM) Area

Explains the DM area for internal data storage and manipulation.

3-6 Holding Relay (HR) Area

Details the HR area for data storage and retention during power interruptions.

3-7 Timer/Counter (TC) Area

Covers TC area for timer/counter programming and access.

3-8 Temporary Relay (TR) Area

Explains the TR area for temporary condition storage in ladder diagrams.

SECTION 4 Writing and Inputting the Program

4-1 Introduction

Introduces program writing, conversion to mnemonic code, and basic steps.

4-2 Instruction Terminology

Defines terminology related to ladder diagram programming instructions.

4-3 The Ladder Diagram

Explains the structure and elements of ladder diagrams.

4-4 The Programming Console

Details the keyboard layout and PC modes of the programming console.

4-5 Preparation for Operation

Outlines procedures for initial setup, password entry, and memory clearing.

4-6 Inputting, Modifying, and Checking the Program

Covers program input, modification, syntax checking, and cycle time display.

4-7 Controlling Bit Status

Explains instructions for controlling individual bit status.

4-8 Work Bits (Internal Relays)

Describes the application and usage of work bits for simplifying programming.

4-9 Programming Precautions

Provides guidelines for drawing clear ladder diagrams and avoiding issues.

4-10 Program Execution

Explains how the CPU cycles through the program for execution.

SECTION 5 Instruction Set

5-1 Introduction

Introduces the K-type PC instruction set and their descriptions.

5-2 Notation

Explains the use of mnemonics and function codes for instructions.

5-3 Instruction Format

Details the structure of instructions, including operands and definers.

5-4 Data Areas, Definer Values, and Flags

Covers data areas, flags affected by instructions, and constant designation.

5-5 Ladder Diagram Instructions

Explains basic ladder and logic block instructions like LOAD, AND, OR.

5-6 Bit Control Instructions

Details instructions for controlling individual bit status like OUT, DIFU, DIFD, KEEP.

5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)

Explains interlock instructions for controlling program flow and execution.

5-8 JUMP and JUMP END – JMP(04) and JME(05)

Describes jump instructions for skipping program sections conditionally.

5-9 END – END(01)

Explains the END instruction, essential for program termination.

5-10 NO OPERATION – NOP(00)

Covers the NOP instruction, which performs no operation.

5-11 Timer and Counter Instructions

Details timer (TIM, TIMH) and counter (CNT, CNTR, RDM, HDM) instructions.

5-12 Data Shifting

Explains instructions for manipulating data in shift registers (SFT, SFTR, WSFT).

5-13 Data Movement

Covers instructions for moving data between memory addresses (MOV, MVN).

5-14 DATA COMPARE – CMP(20)

Explains the CMP instruction for comparing data and affecting flags.

5-15 Data Conversion

Details instructions for converting data between formats (BIN, BCD, MLPX, DMPX).

5-16 BCD Calculations

Covers BCD arithmetic instructions like ADD, SUB, MUL, DIV, STC, CLC.

5-17 Subroutines

Explains subroutine instructions (SBN, SBS, RET) for modular programming.

5-18 Step Instructions

Details STEP and SNXT instructions for sequential and conditional program execution.

5-19 Special Instructions

Covers instructions for I/O refresh, end wait, and notation insertion.

SECTION 6 Program Execution Timing

6-1 Introduction

Introduces program timing, cycle time, and I/O response time.

6-2 Cycle Time

Explains the overall flow of CPU operation and cycle time factors.

6-3 Calculating Cycle Time

Provides examples of calculating cycle time for PC configurations.

6-4 Instruction Execution Times

Lists execution times for all available instructions.

6-5 I/O Response Time

Explains the time taken for PC to respond to input signals.

SECTION 7 Program Debugging and Execution

7-1 Introduction

Introduces procedures for PC program input, debugging, and monitoring.

7-2 Debugging

Covers methods for eliminating execution errors and displaying error messages.

7-3 Monitoring Operation and Modifying Data

Details procedures for monitoring and modifying data in memory areas.

7-4 Program Backup and Restore Operations

Explains how to save and restore program memory data using a cassette tape.

SECTION 8 Troubleshooting

8-1 Introduction

Introduces PC self-diagnostic functions for identifying system abnormalities.

8-2 Reading and Clearing Errors and Messages

Describes how to display and clear system error messages.

8-3 Error Messages

Lists and explains non-fatal and fatal operating error messages.

8-4 Error Flags

Lists SR area flags used for troubleshooting and error identification.

Appendix A Standard Models

CPUs

Lists available K-type C-series CPUs with their specifications.

I/O Units

Details various types of I/O Units available for K-type PCs.

Special Units

Describes Analog Timer Units, Host Link Units, and I/O Link Units.

Mounting Rail and Accessories

Lists mounting rails, brackets, and plates for PC installation.

Factory Intelligent Terminal (FIT)

Describes the FIT computer and its included components.

Graphic Programming Console (GPC)

Lists GPC models, accessories, and interface units.

Appendix B Programming Instructions and Execution Times

Ladder Diagram Instructions

Details basic ladder and logic block instructions with symbols and operands.

Special Instructions

Covers instructions for I/O refresh, end wait, and notation insertion.

Programming Instructions and Execution Times

Lists all K-type instructions with execution times and conditions.

Appendix C Programming Console Operations

Programming Operations

Details operations like address designation, program search, and instruction manipulation.

Debugging Operations

Explains how to read and clear error messages using the console.

Monitoring and Data Changing Operations

Covers bit/word monitoring, forced set/reset, and data modification.

SV Change, SV Reset

Describes methods for changing timer/counter set values (SV).

Cassette Tape Operations

Details procedures for saving, restoring, and comparing program data on tape.

Appendix D Error and Arithmetic Flag Operation

Error and Arithmetic Flag Operation

Table showing which instructions affect ER, CY, GT, LT, and EQ flags.

Appendix E Binary–Hexadecimal–Decimal Table

Binary–Hexadecimal–Decimal Table

Provides a reference table for converting between binary, hex, and decimal values.

About this Manual

Appendix G Program Coding Sheet

Program Coding Sheet

Provides a template for coding ladder diagram programs with addresses and instructions.

Glossary

Revision History

Index

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