Specifications Appendix B
68
CPU Characteristics
Main control elements MPU, CMOS, LSTTL
Programming method Ladder diagram
Instruction length 1 address/instruction, 6 bytes/instruction
Number of instructions 49
Execution time
10 ms/instruction (average)
Memory capacity 1,194 addresses
IR bits I/O bits: 160 (IR 0000 to IR 0915) Max. of 148 usable for I/O
IR 0000 is used for count input and IR 0001 is used for hardware reset
for high-speed counter (HDM(98))
Work bits: 136 (IR 1000 to IR 1807)
IR 1807 is reserved for HDM(98)
SR bits 16 (SR 1808 to SR 1907)
Always ON, Always OFF, battery failure, initial scan ON, 0.1-s clock pulse, 0.2-s
clock pulse, 1.0-s clock pulse, etc.
HR bits 160 (HR 000 to HR 915)
TM bits 8 (TR 0 to TR 7)
DM words 64 (DM 00 to DM 63)
DM 32 to DM 63 are reserved as upper and lower limit setting areas for HDM(98) if it
is used.
Timer/counters 48 (total of TIM’s, CNT’s, and CNTR’s)
TIM 00 to TIM 47 (0 to 999.9 s)
TIMH 00 to TIMH 47 (0 to 99.99 s)
CNT 00 to CNT 47 (0 to 9999 counts)
CNTR 00 to CNTR 47 (0 to 9999 counts)
TC 47 is used for HDM(98). When this instruction is not used, TC 47 can be used for
other purposes.
High-speed counter Count input: IR 0000
Hardware reset input: IR 0001
Software inset: IR 1807
Maximum response frequency: 2 kHz
Preset count range: 0000 to 9999
Number of outputs: 16
Memory protection Status of HR bits, present value of counters, and contents of DM words are retained
during power failure.
Battery life 5 years at 25%C
Battery life is shortened at temperatures higher than 25
°C. Replace battery with new
one within 1 week when ALARM indicator blinks.
Self-diagnostic features CPU failure (watchdog timer)
Memory failure
I/O bus failure
Battery failure, etc.
Program check Program check (executed on start of RUN operation)
END(01) instruction missing
JMP(04)–JME(05) error
Coil duplication
Circuit error
DIFU(13)/DIFD(14) over error
IL(02)/ILC(03) error
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