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CHAPTER 10
10.Digital Input/Output
10.1 OVERVIEW
The RSL10 system contains 16 digital input/output (DIO) pads that can be configured:
• To support the external interfaces, output clocks, and other I/Os
• As general-purpose I/Os controllable from the core
DIOs support all digital inputs and output functions that are not supported directly by a dedicated I/O. For more
information about the functional configuration of DIO pads, see Section 10.2, “Functional Configuration” below.
Dedicated I/Os are supplied for the following pads which are not part of the DIO pad set:
• The wake up pad (WAKEUP)—for more information, see Section 5.4, “Power Modes” on page 51.
• The external clock input pad (EXTCLK)—for more information, see Section 6.2.5, “External Clock Input
(EXTCLK)” on page 76.
• The JTCK and JTMS (also used as SWCLK and SWDIO) pads for the standard SWJ-DP debug port
included with the ARM Cortex-M3 core — for more information, see Section 3.2, “Debug Port” on page 29.
• A reset pad (NRESET) - for more information, see Section 5.5, “Resets” on page 63.
The DIO pads support a variety of physical configuration parameters that might be required to properly interface
with external components, including:
• Pull-up and pull-down resistors
• Low-pass input filtering
• Output drive strength
A complete description of the physical configuration of DIOs can be found in Section 10.3, “Physical
Configuration” on page 265.
All of the DIO pads are powered from the VDDO power supply. For more information about this power supply
and its configuration, see Section 5.2.2, “Digital Output Supply Voltage (VDDO)” on page 40.
10.2 FUNCTIONAL CONFIGURATION
The DIO pads can be configured using the DIO_CFG_IO_MODE bit field from the DIO_CFG_* registers:
• For a variety of digital output modes
• For a general-purpose digital input mode, with the input function configured by the
DIO_interface_SRC
registers, where
interface is one of PCM, SPI, UART, I2C, audio sink, NMI, baseband Rx, baseband SPI,
RF front-end SPI, RF front-end GPIO, DMIC, and LPDSP32 JTAG. For the SPI interfaces, these registers
have a numeric postfix to indicate which of the interfaces is being configured.
Table 18 contains a list of the functional modes a DIO can be configured for. Table 19 contains a list of the input
sources that a given DIO can be assigned to supply.
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