Onkyo C-S5VL - Page 28

Q301: CY2305SXC-1T 3.3V ZERO DELAY BUFFER
C-S5VL
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Logic Block Diagram
PLL
MUX
Select Input
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
CLKOUT
Pin outs
Pin Diagram - CY2305
Pin Description for CY2305
Pin Signal Description
1
REF
[1]
Input reference frequency, 5V-tolerant input
2
CLK2
[2]
Buffered clock output
3
CLK1
[2]
Buffered clock output
4 GND Ground
5
CLK3
[2]
Buffered clock output
6V
DD
3.3V supply
7
CLK4
[2]
Buffered clock output
8
CLKOUT
[2]
Buffered clock output, internal feedback on this pin
1
2
3
4
5
8
7
6
REF
CLK2
CLK1
GND
V
DD
CLKOUT
CLK4
CLK3
Notes
1. Weak pull down.
2. Weak pull down on all outputs.