Onkyo TX-800 - Page 9

Q107
LM7001
(PLL
synthesizer
and
controller)
TX-800
SYCO^A-
XINo^
XOUT<^
fminoUa.
AMIhP%
>
Phase Detector
Charge Pump
—
*-£>o~
—
Reference Divider
r^n I
*
T^
Vn
'
:
Tfr
A
Programable
Divider
1'
&u
n
—
oPD1
<&>PD2
Shift Register
•
Latch
CE
CL
DATA
W<M
n
sx 9
,12.
•VDD1
H
£oVDD2
>V5S
Pin
No.
1
10
11
12
13
14
15
16
Terminal
XOUT
XIN
CE
CL
DATA
Description
Connect
to
the
7.2 MHz
crystal
oscillator.
Chip
enable
terminal.
Connect
to
the
PLL
terminal
of micro
processor.
Serial
clock
input
terminal.
Connect to
the CLOCK
terminal of
microprocessor.
Serial
data input
terminal.
Connect
to the DATA
terminal
of
microprocessor.
SYN
BOl
B02
B03
AMIN
FMIN
VddI
Vdd2
PD1
PD2
Vss
Not
used.
Not used.
FM
control
signal
output
terminal.
"L"
when FM.
AM
control
signal
output
terminal.
"L"
when
AM.
AM local
oscillator
input
terminal.
FM
local
oscillator
terminal.
Power
supply
terminal
for
back-up.
Power
supply
terminal.
Charge
pump
output
of
the
phase
detector
which
constitutes
the
PLL.
High
level
is
output
when
the
divided
local
oscillator
frequency
is
high
than
the
reference
frequency.
In
the
opposite
case,
low level
is output.
Floating
occurs
when
the
frequencies
matched.
The
output
is
applied
to
the
variable
capacitor
diode
in
the
local
oscillator
through
the
low
pass
filters.
Ground
terminal.
-9-