(NOTE:
Because
the compressor/limiter control
loop "looks at" the
predistorted
output
of 1C
14
rather
than the actual
output
level
of fhe VCA (at
IC9B),
when
attempting to increase
gain with R64, you
will observe that the VCA output level
does not
necessarily increase in proportion to the control calibrations.
You will note
that
instead,
the
gain
reduction increases due
to
the non-proportional increase
in
the
peak output
level
of
1C 14
compared
to
the
output
level
of the VCA. This
circuit feature
helps the system resist clipping as the
VCA
overload point
is
approached.)
The
output
of the
multiplier
is the output of
1C I
A, which feeds the ATTACK
TIME
control as
discussed
above.
It can thus
be
seen that
all of the many other
threshold modifications discussed above in association with the
ATTACK
TIME and
RATIO controls
are
scaled
proportionately
by the action of the multiplier,
as
desi red.
Gating Circuitry:
The gating detector monitors the level
of the
424A
input
signal,
and
activates
the
gate
if said level drops below a threshold adjustable with the
GATE THRESH control RI4.
The
gate is
activated when the
output of ICI8B is
positive,
and
defeated when it is negative.
The
input
level
detector
is a
half-wave
positive peak detector, and consists
of
ICI8A and associated
components. The input line is connected to the
(+)
input
of
ICI8A.
ICI8A's output
charges
C7
through
CRI
and R6. The voltage
across C7
is
fed back to !CI8A's (-)
input through voltage divider
R7, R8,
which
also serves
to
discharge
C7
in the absence of
signal, thus
determining the recovery time
of
the
detector.
The
choice
of
components
yields
a
DC
detector gain
of
approximately 22x.
The voltage at
C7
(representing
22x the positive peak value
of
the 424A input
signal after
the
INPUT
ATTEN)
is applied to the
(-) input
of
1CI8B,
operated
as
a
comparator
with hysteresis. The comparator
threshold is a voltage developed at
ICI8B's
(+)
input
through resistor network
R9, R 1
1 ,
RI2, RI3, RI4.
When the
voltage at
ICI8B's
(-)
input
is lower than the voltage at
its
(+)
input, ICI8B's
output goes
positive
and
the gate turns
on.
Feedback
for
hysteresis
is
provided
through
R
I I . The
positive
threshold voltage
at
ICI8B's
(+)
input is adjusted by
means of RI4.
R9
is
connected
to
the
-15
volt
supply, and assures
that turning
RI4
fully counterclockwise will force the
voltage at
1C 1 8B's
(+)
input slightly negative
,
thus
turning
the gating function off
since
the
voltage across C7 (applied to ICI8B's
input)
can
never
go negative.
Under gated conditions, Q4
is
pinched off
by
pulling
its gate to a
high positive
voltage through CR22. This
opens
the
RELEASE TIME path and
permits the
IDLE
GAIN control R72
to
inject
a
voltage into R70 which forces the output voltage of
the timing module
to
drift towards the voltage
at
the wiper
of
the IDLE GAIN
control.
Under ungated conditions,
CR22
is OFF,
Q4's
gate is clamped
to the
same
voltage
as its
source through R74, and
Q4
becomes equivalent
to
a
low
resistance. Since
Q4's
source is driven from a low impedance, the effect of the IDLE GAIN
control
is entirely swamped out, and the RELEASE TIME control is permitted to conduct
normally.
Gain Reduction Meter: The gain-control voltage
at
the output
of
the
timing
module is
fed
fo a peak-detector
circuit (consisting of 1C
16 and associated
components) which
in
turn
drives the gain reduction meter.
37
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