Panasonic CQ-C3203U - Page 7

Pin
No.
Port Description I/O (V)
FM AM CD
1 XIN Crystal oscillator I 2.5 2.5 2.5
2 TEST2 Ground I 0 0 0
3 VREG Bypass condenser
connected.
O 2.9 2.9 2.9
4
VSSCPU
Ground - 0 0 0
5 NC - - - - -
6 NC - - - - -
7 NC - - - - -
8 NC - - - - -
9 LCD
DO
LCD data output I 5 5 5
10 LCD DI LCD data input O 4.9 5 4.9
11 LCD
CLK
LCD clock O 5.1 5.1 5.1
12 LCD CE LCD chip enable
output
O 0 0 0.3
13 CD DO CD data output I 5.1 5.2 4
14 CD DI CD data input O 0 0 4.6
15 CD
CLK
CD clock O 4.9 49 4.9
16 CD CE CD chip enable O 0 0 1
17 CD LM
(+)
CD loading motor
control
O 0 0 0
18 CD LM
(-)
CD loading motor
control
O 0 0 0
19 CD S/L CD spindle motor
control
O 5.1 5.1 5.1
20 SUB
READY
Sub CPU ready
signal
I 0 0 5
21 CD
INSW1
CD insert SW input I 0 0 0
22 CD
SW2
CD mechanism
SW2
I 5.1 5.1 0
23 CD
LIMIT
SW
CD limit SW I 0.2 0.2 5.1
24 CD
MUTE
CD Mute signal I 5.1 5.1 5.1
25 CD RST CD reset O 5.1 5.1 5.1
26 CD
DMUTE
CD mute O 0 0 5.1
27 LOW
BATT
Battery low level
detect
I 5.1 5.1 0
28 NC - - - - -
29
PANEL
Panel
detect
switch
I
0
0
0
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