Panasonic SY-PA100

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42
41
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1
2
3
4
5
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8
9
10
11
12
13
14
15
16
17
18
19
20
2122232425262728293031323334353637383940
BCLK
LRCK
SRDATA
DV
DD1
DVss1
TX
MCLK
MDATA
MLD
SENSE
/FLOCK
/TLOCK
BLKCK
SQCK
SUBQ
DMUTE
STAT
/RST
SMCK
CSEL
TRV TVD PC ECM ECS KICK TRD FOD
VREF
FBAL TBAL FE TE RFENV VDET OFT TRCRS /RFDET BDO LDON
PLLF2
DSLF2
WVEL
ARF
IREF
DRF
DSLF
PLLF
VCOF
AV
DD2
AVss2
EFM
PCK
VCOF2
SUBC
SBCK
Vss
X1 IN
X2 OUT
V
DD
BYTCK
/CLDCK
FCLK
IPFLAG
FLAG
CLVS
CRC
DEMPH
RESY
IOSEL
/TEST
AV
DD1
OUTL
AVss1
OUTR
RSEL
IOV
DD
PSEL
MSEL
SSEL
191817161514
1
32 4 5 6 7 8 9 10 11 12 13
TP22
A
B
TP23
TP21
C727
50V1
C728
50V1
C725
1000P
C726
1000P
R718
1K
R717
1K
C754
470P
C730
0.1
C731
10V220
R721
100
C732
10V220
C733
0.1
TP20
C753
470P
A
B
CN702
C743
0.1
TP14TP13TP8 TP12TP6 TP7TP4TP3
IHGFEDCB
S701
(REST SW)
TP16
C745
1000P
A
B
C
D
E
F
G
H
I
GFEDCBAIHG F EDCBA
R712
220
C718
0.22
C717
0.1
C744
5600P
R709
47K
R741 47K
R711
82K
C722
10P
X701
(16.9344MHz)
C721
10P
C724
0.1
C723
10V220
IC702
MN662790RSC
SERVO PROCESSOR/
DIGITAL SIGNAL PROCESSOR/
DIGITAL FILTER/
D/A CONVERTER
+B(2)
Rch OUT
/RST
STAT
SUBQ
SQCK
BLKCK
P.GND
MLD
MDATA
MCLK
TX
LD SW
D.GND
A.GND
Lch OUT
REST SW
SPEED
R753
10
TP15
TP1
R742
220K
KJ
+B(1)
A
TP17
TP19
R714
0
SY-PA100
CD SERVO SCHEMATIC DIAGRAM
SCHEMATIC DIAGRAM - 17
To CPL CD-LCD CIRCUIT(CN2) on SCHEMATIC DIAGRAM - 10
B
6.9V
3.4V
3.4V
3.4V
3.4V
1.6V
(3.1V)
(0.3V)
3.4V
0V
3.4V
0V
3.4V
3.3V (3V)
0V (3.3V)
3.4V
1.7V 3.3V(0V) 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V
1.7V
1.7V 3.3V(0V)
0V(3.3V)
0V 0V
1.7V
1V
1.7V
0V
3.4V
1.6V
1.6V
3.4V
3.4V
3V
1.5V
3.4V
1.5V
3V
PLAY
1kHz, 0dB
2.2V
P-P
0.7V
P-P
F=16.9344MHz
PLAY
0.7V
P-P
PLAY
2ms. 0.1V/DIV.
0.4V
P-P
PLAY
0.1V
P-P
2ms. 0.1V/DIV.
PLAY
0V
3V
T 13.3ms.
PLAY
0V
3V
T 13.3ms.
PLAY
0V
3V
T 13.3ms.
0.5 s. 0.2V/DIV.
3.4V
2V
P-P
F=16.9344MHz
3.4V 3.4V
1.5V
1.7V
3.4V
0V
PLAY
0V
3.3V
F=75Hz
PLAY
0V
3.3V
T 13.3ms.
:+B VOLTAGE LINE :CD SIGNAL LINE