C
1
1
1
1
1
SYSB
SYSA
TXP
TXN
RXP
RXN
REF
ATA
CLKIN
DP
DM
REF
C1A
C2A
BYTECLK
BYTECLKVALID
PACKETCLK
ERROR
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
TSIN1
TSIN1DATA
0
1
2
3
4
5
6
7
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
TSIN2
TSIN2DATA
4
5
6
7
PIO5
0
1
2
3
4
5
6
7
PIO4
0
1
2
3
4
5
TRIGGER
SYSITRQ
TSIN0
TSIN0DATA
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PIO1
0
1
2
3
4
5
6
7
PIO0
USB
DAA
0
1
2
3
4
5
6
7
0
1
2
3
SYSBCLKOSC
SYSBCLKINALT
SYSCLKOUT
RTCCLKIN
TMUCLK
RSETIN
WDOGRSTOUT
ASEBRK
IN
OUT
0
1
2
3
NMI
TDI
TMS
TCK
TRST
TDO
6
7
PIO3
0
1
2
3
4
5
6
7
PIO2
1
742
2008-03-17
ROYAL PHILIPS ELECTRONICS N.V. 2008
SV
2008-09-05
DC320600
Li LingHuan
2008-03-17
2
3
DATE
13010
12008-03-17
-- -- --
-- -- --
A2
TV522
PCB SB SSB TV522/22M-1080P_2
CHN
3139 123 6423
CHECK
NAME
2
SUPERS.
1
CLASS_NO
SETNAME
3PC332
MODE[13]
7
3A48 B6
3A16 B6
EMI banks port size at boot
3A30-3 F2
IA29 B7
IA2B E11
BD 12NC : 3139 123 63411 / 63711
IA19 A2
IA20 C3
IA21 C5
7A10-3 B6
7A10-4 B2
3A25-2 C9
3A25-3 C8
3A25-4 C9
Long resetout mode
3A29-1 E2
5A10 A2
3A49 B6
3AC8-4 D11
3A44 C11
3A45 C12
STI7100 : Control
3A30-1 F2
3A31-2 G2
3A31-4 G2
A
B
C
D
3A32-1 G2
3A30-4 F2
3A35 G2
E
3A31-3 F1
3A11 D9
3A12 C9
MODE[3:2]
3A36-1 H2
Reserved
IA2C E11
3A43 B7
910
IA2A D11
3A46 A6
3A36-2 H2
RES
3A02 D11
RES
3A23 A9
3A20 A8
3A24 A9
3A25-1 C8
3A18 B9
MODE[10]
F
G
H
USED FOR IPTV
2A21 C6
2A22 C3
IA16 B4
EMIADDR[4:3]
8 96
IA11 D9
3A29-4 E2
FA10 B7
IA10 C9
IA18 C4
7A10-1 B3
7A10-2 B4
RES
7A10-6 C2
7A10-5 C2
3A26 B6
3A27 C4
3A28 C4
10 11 12 13
3A14 B9
7A00-4 A10
2A19 A2
2A20 A3
3A15 C9
3A4A E11
Reserved
EMIADDR[10:9]
3A13 C9
3A47 A6
PLL1 startup configuration
3A32-3 H2
Mode pin
3A30-2 F2
3A10 E9
2
3A22 A9
3A19 G1
RES
RES
7 8
IA27 G11
IA24 B9
2A23 C4
2A24 F11
2A25 F11
3A01 D12
13
EMIADDR[2:1]
3 4
Purpose
5
MODE[7:4]
1
PCMOUT4 STx71000 master/slave mode
PCMOUT2
" XA00 ~ XA4Z "
IA17 B5
3A29-2 E2
EMI pin
3A29-3 E2
Reserved
EMIADDR[14]
MODE[16]
9A31 F11
EMIADDR[15]
MULTI 12NC : 3139 123 63401 / 63701
9A29 B9
9A22 C5
9A30 B9
9A21 B5
A
B
G
RES
1A10 C4
2A18 A2
E
F
EMIADDR[8:5]
C
D
Reserved
H
3A33 B11
3A34 F11
1
IA28 F11
IA23 B11
IA26 F11
PCMOUT3
IA22 C5
EMIADDR[13:12]
IA25 C11
PLL0 startup configuration
CELL 12NC : 8239 125 14401
MODE[1:0]
MODE[9:8]
56
43
11 12
2
Reserved
MODE[14]
FA11 B9
MODE[12:11]
MODE[15]
1110
54
3
2
19
18
3A17 B7
3A21 G2
I
H
C
B
A
541
12
RES
7A12 C4
17 18 19 20
141312987
6
A
B
C
D
1 20
G
H
171615
All rights reserved. Reproduction in whole or in parts
is prohibited without the written consent of the copyright
P
O
N
M
L
K
J
I
J
L
M
N
O
P
2 3
owner.
K
678 91011
IA21
E
F
G
F
E
D
13 14 15 16
IA11
3A28
560R
RES
7A10-1
74LVCU04APW
1
714
2
3A33
1K5
+2V5
+3V3
V_LVC04
10K
3A25-2 2 7
3A48
10K
10K
3A10
IA19
V_LVC04
10K
1 8
3A32-1
9A22
IA22
+3V3
3A23
10K
10K
3A49
3A01
10K
3A02
100R
220R
5A10
V_LVC04
IA10
14
12
7A10-6
74LVCU04APW
13
7
3A32-3
10K
3 6
3A34
470R
3A46
10K
1n0
2A20
IA25
IA23
100R
3A45
3A44
100R
FA10
9A21
RES
27M
1A10
RES
9A31
3A20
10K
RES
3A19
10K
+3V3
3A4A
+3V3
33R
100n
2A18
3A25-1
10K
1 8
10K
3A22
V_LVC04
3A26
68R
7A10-5
74LVCU04APW
11
714
10
IA2A
IA29
45
10K
3A31-4
10K
3A24
2A22
18p
RES
7
3A36-2
10K
2
3A29-2
27
10K
3A16
10K
10K
3A17
9A29
+3V3
3A15
10K
33R3AC8-4 45
2A21
15p
1M0
RES
45
3A27
3 6
10K
3A25-4
45
3A25-3
10K
10K
3A29-4
9A30
RES
3A29-1
10K
1 8
18p
2A23
IA18
IA17IA16
IA27
3A12 10K
27
10K
3A31-2
3A30-1
1 8
10K
2A25
10n
IA26
+3V3
IA24
100n
V_LVC04
IA20
2A19
10K
3A35
FA11
10K
3A43
IA2C
IA28
3A13
10K
3
714
4
+3V3
14
8
7A10-2
74LVCU04APW
7A10-4
74LVCU04APW
9
7
3A11 10K
3A31-3
10K
10K
27
3 6
3A30-2
10K
3A30-3
3A21
10K
74LVCU04APW
5
714
6
7A10-3
10K
3A47
3A14
22R
10n
2A24
10K
3A18
3A30-4
10K
45
3 6
1 8
10K
3A29-3
1
4
3
10K
3A36-1
7A12
27M
2560TK
2
AN25
AM25
E19
IA2B
AN2
AN1
AM2
AM1
AL2
AL1
AL3
AP2
AP3
AP25
AD5
AC4
AC5
AB4
AB5
AA4
AE4
AF4
AM3
AN3
AP1
AK2
AJ1
AJ2
AH1
AH2
AH4
AJ4
AG5
AF5
AE5
AD4
E22
E21
E18
D17
D18
AK6
AJ5
AH5
AG4
AK1
C1
AP27
E27
AN27
E17
AK25
AK26
AK27
AK28
D21
D22
AB31
AA30
AB33
AA34
AA33
Y34
Y33
AA31
Y30
Y31
D16
AD33
AC34
AC33
AB3
4
AD32
AD30
AD31
AC30
AC31
AB30
AJ31
AH30
AH31
AG30
AG31
AE31
AE30
AE32
AE34
AE33
AD34
AM34
AL32
AL34
AL33
AK34
AK33
AJ34
AJ33
AH34
AH33
AJ30
E16
E20
D19
D20
AM32
AP33
AN33
AP34
AN34
AM33
AM3
0
AP31
AN31
AP30
AN30
AN5
AP5
BUF-RST-TARGETn
LAN-RST
PHY-CLK
MII-RX-ER
7A00-4
STI7101BWC
Φ
DIGITAL
INTERFACE
PCMOUT2
PCMOUT3
TSI1-ST-D5
TRIG-IN
JTAG-TMS-ST
JTAG-TCK-ST
JTAG-TRSTn-ST
JTAG-TRSTn-ST
JTAG-TCK-ST
JTAG-TMS-ST
JTAG-TDI-ST
WP-FLASH-ST
EMI-A9
PCMOUT4
EMI-A13
EMI-A12
EMI-A14
EMI-A15
EMI-A4
EMI-A1
EMI-A2
27MHZ-3V3
EMI-A14
TMUCLK
JTAG-TDI-ST
JTAG-TDO-ST
EMI-A3
EMI-A8
EMI-A7
EMI-A6
EMI-A5
EMI-A10
BOLT-ON-IO_RESET-STI7100
CPU-27MHZ
TMUCLK
TRIG-IN
TRIG-OUT
27MHZ-3V3
CPU-27MHZ
RXD-ASC2
TXD-ASC2
TSI1-ST-CLK
TSI1-
ST-VAL
TSI1-ST-D0
TSI1-ST-D1
TSI1-ST-D2
TSI1-ST-D3
TSI1-ST-D4
TSI1-ST-D6
TSI1-ST-D7
TSI1-ST-STRT
SCL-SSB
SDA-SSB
ASEBRKn
JTAG-TDO-ST
TSI0-ST-CLK
TSI0-ST-VAL
TSI0-ST-D0
TSI0-ST-D1
TSI0-ST-D2
TSI0-ST-D3
TSI0-ST-D4
TSI0-ST-D5
T
SI0-ST-D6
TSI0-ST-D7
TSI0-ST-STRT
18680_506_090827.eps
090827
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