Philips 40PFL7007H/12 - Diagram 10-2-7 B02 A, Tuner-Channel Decoder B02 A, CXD2834 (IC7 KC0); Internal Block Diagram and Pin Configuration

IC Data Sheets
EN 54 QFU1.1E LA8.
2012-Sep-14
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8.1 Diagram 10-2-7 B02A, Tuner-channel decoder B02A, CXD2834 (IC7KC0)
Figure 8-1 Internal block diagram and pin configuration
19220_025_120227.eps
120227
Block diagram
Pinning information
TSIF
I
2
C IF
SCL
SDA
RFAIN
TTUSCL
TTUSDA
TAINP (IF)
TAINM (IF)
GPIO1 (PWM)
TIFAGC
XTALI
XTALO
41MHz or
20.5 MHz
IF+
IF-
(RFAGC-MON)
(RFAGC)
IFAGC
SCL
SDA
TUNER
MPEG
Decoder
TSCLK
TSVALID
TSSYNC
TSDATA7-0
TSCLK
TSVALID
TSSYNC
TSDATA7-0
SCL
SDA
DVB-T2
Demodulator
LDPC/BCH
Decoder
Stream
Processor
RS Decoder
TS
Smoothing
DVB-T
Demodulator
DVB-C
Demodulator
OSC
PLL
10-bit
ADC
12-bit
ADC
AGC
GPIO