Circuit Descriptions
EN 56 Q552.1E LA7.
2010-Feb-19
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Figure 7-17 LED grouping per board
The communication between PNX85500, Complex
Programmable Logic Device (CPLD) and the Ambilight module
uses the SPI protocol; refer to figure 7-18 Communication
protocol outside LED board. Between the CPLD and the LED
driver, as “extra” line is mentioned:
• Non-SPI signals that are required for the LED driver
• Temperature sensor line.
Figure 7-18 Communication protocol outside LED board
Refer to figure for an overview of the communication inside the
LED board.
Figure 7-19 Communication protocol inside LED board
The buffer is built around item no. 7B20 (diagram AL1A) and
regenerates the clock signals. Refer to figure 7-20 Ambilight
buffer.
Figure 7-20 Ambilight buffer
The temperature sensor is built around item no. 7B30 (diagram
AL1A) and indicates overtemperature of the board. Refer to
figure 7-21 Temperature sensor
.
Figure 7-21 Temperature sensor
The EEPROM (item no. 7B07; diagram AL1A) contains
alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
to figure 7-22 EEPROM
.
Figure 7-22 EEPROM
The LED driver is built around item no. 7B26 (diagram AL1A)
and controls the LEDs. Refer to figure 7-23 LED driver
.
18770_210_100126.eps
100126
3
×
6
L
E
D
18
4
×
6
L
E
D
24
5
×
6
L
E
D
30
4
+
5
L
E
D
9
2
×
6
L
E
D
12
3
×
5
L
E
D
15
6
×
6
L
E
D
36
18770_211_100126.eps
100126
CPLD
PNX
SPI S PI + extra
1M59
18770_213_100126.eps
100219
LED
Driver
EEPROM
Buffer
SPI S PI
SPI
SPI
SPI
1M83
1M84
Extra
Tem p
sens or
Tem p
18770_214_100126.eps
100126
+3V3
8
3B30-1
220R
1
45
220R
3B30-43B01-1
100R
1 8
5
6
7B20-1
74LVC2G17
1
2
2B17
100n
33p
2B01
100R
3B01-2
27
100p
2B02
+3V3
3
25
4
74LVC2G17
7B20-2
33p
2B00
2B10
100p
PWM-CLOCK
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
18770_215_100126.eps
100126
-T
+3V3
10n
2B09
FB40
2B08
10n
1K5 1%
3 6
3B39-2
27
3B39-3
1%1K5
1
3
4
52
LMV331IDCK
7B30
+3V3
1K5 1%
8 1
3B39-1
3B34
RES
100K
10K
3004
RES
3B11
10K
+3V3
FB41
TEMP-SENSOR
18770_216_100126.eps
100126
S
GND
Q
HOLD
W
VCC
C
D
+3V3
4
1
2
3 5
7B06
74LVC1G32GW
2B20
100n
4
7
2
1
8
3
+3V3
M95010-WDW6
7B07
(64K)
Φ
6
5
+3V3
10K
3B02-2
27
1 8
3B02-1
10K
+3V3
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH