Philips 42HFL5682D/F7 - Page 34

IC Data Sheets
EN 34 TPB1.2HU LA8.
2011-Mar-11
8.3 Diagram B01 SMB: 32-bit DDR Term/Conn, BCM3549L (IC U1)
Figure 8-4 Internal block diagram
18890_303_101008.eps
101008
Block diagram
SPDIF
Dual LVDS
ITU656
Svideo, CVBS
2 HDMI
Component 1
DS_IF
Video Front
End
5x 10bit A/Ds
Dual HDMI
Receiver
RGB + HV
Svideo 1
Composite 1
12bit A/D
NTSC/PAL/SECAM
Demod +
BTSC Decoder
A2 Decoder
NTSC Video Decoders
VBI Decoder
QAM/VSB Demod
AVC/MPEG 4/VC-1/MPEG 2
Transport Processor
with DVB/DES
AVC/MPEG 4/VC-1/MPEG 2
HD/SD Video Decoder
3D Graphics
2x Video
DACs
Audio
DACs
Peripherals
Keypad LED
GPIO
3 UARTS
Dual USB 2.0
Ethernet
MIPS DUAL CORES
32KI/32KI & 64KD
128KB L2
400MHz
SPI & Nand
Flash Interfaces
EIA/CEA
909
I2S
SPDIF
T P X
C
F
I
4 9
3
1
I2S (dual)
L/R Audio
HD/SD Video
Encoder
Video & Graphics
Processing (BVN)
HD Analog Noise
Reduction
Digital Noise Reduction
Picture Enhancement
Processor
3D
Comb
Motion Adaptive
1080i De-interlacing
2
Component 2
Svideo 2
Composite 2
Programmable
Audio
DSP
L/R Audio
JPEG Decoder
Audio
Switch
and A/D
6 Audio L/R
Composite 3
Composite 4
Svideo 3
Component 3
SIF
DDR2 Memory
Interface 32 bits
– 800/1066 MHz
2 R D D
DVR Engine
L/R Audio
ITU 656