SAA7324 – DECODER, DIGITAL SERVO IC AND D/A-CONVERTER CD10 (low voltage version)
Pin Name Direction Description
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1 HFREF → CD10 comparator common mode input
2 HFIN → CD10 comparator signal input
3 ISLICE CD10 → current feedback from data slicer
4 VSSA1 GND analog ground 1
5 VDDA1 +3 analog supply voltage 1
6 IREF CD10 → reference current output pin
7 VRIN CD10 → reference voltage for servo ADC’s
8 D1 HF-preamp → CD10 unipolar current input (central diode signal input)
9 D2 HF-preamp → CD10 unipolar current input (central diode signal input)
10 D3 HF-preamp → CD10 unipolar current input (central diode signal input)
11 D4 HF-preamp → CD10 unipolar current input (central diode signal input)
12 R1 HF-preamp → CD10 unipolar current input (satellite diode signal input)
13 R2 HF-preamp → CD10 unipolar current input (satellite diode signal input)
14 VSSA2 GND analog ground 2
15 CROUT CD10 → X-TAL crystal/resonator output
16 CRIN X-TAL → CD10 crystal/resonator input
17 VDDA2 +3 analog supply voltage 2
18 LN CD10 → DAC left channel differential output - negative
19 LP CD10 → DAC left channel differential output - positive
20 VNEG → CD10 DAC negative reference input
21 VPOS → CD10 DAC positive reference input
22 RN CD10 → DAC right channel differential output - negative
23 RP CD10 → DAC right channel differential output - positive
24 SELPLL +3 selects whether internal clock multiplier PLL is used
25 TEST1 GND test control input 1; this pin should be tied low
26 CL16 CD10 → 16.9344 MHz system clock output
27 DATA CD10 → serial data output (3-state)
28 WCLK CD10 → word clock output (3-state)
29 SCLK CD10 → serial bit clock output (3-state)
30 EF CD10 → C2 error flag output (3-state)
31 TEST2 GND test control input 2; this pin should be tied low
32 KILL CD10 → kill output (programmable; open-drain)
33 VSSD1 GND digital ground 2
34 V2/V3 CD10 ↔ versatile I/O: input versatile pin 2 or output versatile pin 3 (open-drain)
35 WCLI → CD10 word clock input (for data loopback to DAC)
36 SDI → CD10 serial data input (for data loopback to DAC)
37 SCLI → CD10 serial bit clock input (for data loopback to DAC)
38 RESETn µP → CD10 power-on reset input (active low)
39 SDA µP ↔ CD10 microcontroller interface data I/O line (open-drain output)
40 SCL µP → CD10 microcontroller interface clock line input
41 RAB → CD10 microcontroller interface R/W and load control line input (4-wire bus mode)
42 SILD µP → CD10 microcontroller interface R/W and load control line input (4-wire bus mode)
43 STATUS CD10 → servo interrupt request line/decoder status register output (open-drain)
44 TEST3 GND test control input 3; this pin should be tied low
45 RCK → CD10 subcode clock input
46 SUB CD10 → P-to-W subcode bits output (3-state)
47 SFSY CD10 → subcode frame sync output (3-state)
48 SBSY CD10 → subcode block sync output (3-state)
49 CL11/4 CD10 → 11.2896 MHz or 4.2336 MHz (for microcontroller) clock output
50 VSSD2 GND digital ground 3
51 DOBM CD10 → bi-phase mark output (externally buffered; 3-state)
52 VDDD1P +3 digital supply voltage 2 for periphery
53 CFLG CD10 → correction flag output (open-drain)
54 RA CD10 → servo driver radial actuator output
55 FO CD10 → servo driver focus actuator output
56 SL CD10 → servo driver slide control output
57 VDDD2C +3 digital supply voltage 3 for core
58 VSSD3 GND digital ground 4
59 MOTO1 CD10 → servo driver motor output 1; versatile (3-state)
60 MOTO2 CD10 → motor output 2; versatile (3-state)
61 V4 CD10 → versatile output pin 4
62 V5 CD10 → HF-gain switch versatile output pin 5
63 V1 inner switch → CD10 versatile input pin 1
64 LDON CD10 → HF-preamp laser drive on output (open-drain)
3-2
CS 46 647
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