5.2.3 Low level test implementation
The low level test (short: lltest) is implemented in the boot
part of the CD-ATOS software. The whole test occupies
about 15k of ROM memory and is written
in
assembler. The
test runs without the use of any external RAM. It only uses
internal CPU registers. As communication channel the
68070's UART is used. Before starting the normal player
boot the following sequence is executed :
1.
Initialize the 68070's UART : 9600 baud
1 startbit
2.
Clear the RXD buffer.
3.
Wait 5
ms.
4.
Read the RXD buffer.
8 databits
1
stopbit
no parity
no handshake
!
If
the character receved was a space ($20) the start
the terminal lltest.
If the character received was an ACK ($06) the start
the pcb I ltest.
5.
Else start the normal player boot.
The UART is connected to
1/0
port 2
5.2.4 How to start up the low level test
With service pcb
To startup
the pcb low level testsoftware
the next
sequence should be followed:
- Switch off the player.
- Connect service pcb to port 2 at the rear of the player.
- Switch
on
the player.
- The service pcb display should now show 'CDI
Rlxx'.
(with xx the release number)
- The pcb lltest is now ready to go.
With VT100 terminal
To
startup
the terminal low level testsoftware
one should
follow the next sequence:
- Switch off the player.
- Connect the terminal to the 68070's UART of the player.
- Switch on the player while pressing the SPACE-bar of the
terminal.
- The terminal should now show the title of the terminal
lltest.
5.2.5 PCB low level test
If the service pcb
is
connected to port 2 the pcb low level
test is executed after power on.
In
table 1 a survey is given
for all tests executed.
Display lltest release number:
When this lltest is entered, first the release number of the
pcb lltest will be displayed.
Example:
CDI
Rlxx
( RL stands for RELEASE, xx stands for release
x.x).
PCS
67639
The lltest is now waiting for an action from the user.
The user should now press either the'Y' or 'N' button to
continue the test.
STEP0:
VDSC
STEP 0A0B : VDSC channel 1 &2 registers
display:
OA0B
In
this step some registers of the VDSC Channel 1
&2
are
initialized.
STEP1:
ROM
In
this step the contents of the ROM is checked.
Following tests are done on the ROM :
1.
Display ID byte and release number of this ROM.
(test
A)
format 'IDxxRLyy'
3.
Check if the parity of the ROM
is
OK.
(test C)
STEP
1:
ROM
STEP
1A:
ID AND RELEASE NUMBER DISPLAY
display: 1 A IDxxRLyy
·
In
this step the release number of this ROM is displayed for
a moment.
(ID stands for IDentification, xx is the id number.
RL
stands for RELEASE, yy stands for y.y)
STEP1C:CHECKSUM
display: 1C
In thls step the checksum of this ROM is calculated as
described in "how is the checksum calculated". If the
checksum is not ok
an
error will be displayed.
display: 1 C Er05
STEP
5 :
NVRAM
The nvram test is a non destructive test. This means that
the original nvram contents is restored again.
Address range : Full nvram address range
display: 5
The following actions take place in the nvram test:
1.
read byte from nvram and save it
in
a register
2.
write a pattern (from ROM) to nvram
3.
read byte from nvram and compare with pattern
4.
if byte read is ok then continue with action 5 else
give error message and stop testing
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