Progressive Scan
The progressive scan section is integrated into
the Digital Board and built around the SAGE
Fli2200 Deinterlacer/Line Doubler (7700). Refer
to Figure 40. This I
2
C controlled device uses
64Mbit SDRAM (32bit x 2M) to perform high
quality de-interlacing (meshing). The
Deinterlacer gets his Digital YUV input data, Pins
20-27, from 7200. The format of the Digital YUV
input is CCIR656 with separated H sync, V Sync.
Because the 7200 doesn’t have a V sync output
the odd/even output of this IC has to be translat-
ed to a V sync signal. Vertical sync is generated
with a flip-flop IC7701 and an XOR, 7702.
Power and Clocks
IC7701 uses two supplies, 3.3Vdc and 2.5Vdc.
The system clock, SYSCLK_PROGSCAN is run-
ning at 27Mhz.
7701 produces three 8 bit output signals, Y, Cr
and Cb. These are sent to the D/A converter
7801.
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